CY7C66113C-LFXCT Cypress Semiconductor Corp, CY7C66113C-LFXCT Datasheet - Page 24

• Manufacturer Part Number: CY7C66113C-LFXCT
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Bit 7: MSTR Mode
Setting this bit to 1 causes the I
master mode transaction by sending a start bit and transmitting
the first data byte from the data register (this typically holds the
target address and R/W bit). Subsequent bytes are initiated by
setting the Continue bit, as described later in this section.
Clearing this bit (set to 0) causes the GPIO pins to operate
normally. In master mode, the I
the clock (SCK), and drives the data line as required depending
on transmit or receive state. The I
any required arbitration and clock synchronization. IN the event
of a loss of arbitration, this MSTR bit is cleared, the ARB Lost bit
is set, and an interrupt is generated by the microcontroller. If the
chip is the target of an external master that wins arbitration, then
the interrupt is held off until the transaction from the external
master is completed.
When MSTR Mode is cleared from 1 to 0 by a firmware write, an
I
Bit 6: Continue/Busy
This bit is written by the firmware to indicate that the firmware is
ready for the next byte transaction to begin. In other words, the
bit has responded to an interrupt request and has completed the
required update or read of the data register. During a read this
bit indicates if the hardware is busy and is locking out additional
writes to the I
the hardware to complete certain operations that may require an
extended period of time. Following an I
compatible block does not return to the Busy state until firmware
sets the Continue bit. This allows the firmware to make one
control register write without the need to check the Busy bit.
Bit 5: Xmit Mode
This bit is set by firmware to enter transmit mode and perform a
data transmit in master or slave mode. Clearing this bit sets the
part in receive mode. Firmware generally determines the value
of this bit from the R/W bit associated with the I
packet. The Xmit Mode bit state is ignored when initially writing
the MSTR Mode or the Restart bits, as these cases always cause
transmit mode for the first byte.
Document Number: 38-08024 Rev. *D
2
C Stop bit is generated.
2
C Status and Control register. This locking allows
2
2
C compatible block to initiate a
C compatible block generates
2
C compatible block performs
2
C interrupt, the I
2
C address
2
C
Bit 4: ACK
This bit is set or cleared by firmware during receive operation to
indicate if the hardware should generate an ACK signal on the
I
(SDA LOW) on the I
During transmits (Xmit Mode = 1), this bit should be cleared.
Bit 3: Addr
This bit is set by the I
a slave receive transaction, after an I
bit is cleared when the firmware sets the Continue bit. This bit
allows the firmware to recognize when the master has lost
arbitration, and in slave mode it allows the firmware to recognize
that a start or restart has occurred.
Bit 2: ARB Lost/Restart
This bit is valid as a status bit (ARB Lost) after master mode
transactions. In master mode, set this bit (along with the
Continue and MSTR Mode bits) to perform an I
sequence. The I
to the data register before setting the Continue bit. To prevent
false ARB Lost signals, the Restart bit is cleared by hardware
during the restart sequence.
Bit 1: Receive Stop
This bit is set when the slave is in receive mode and detects a
stop bit on the bus. The Receive Stop bit is not set if the firmware
terminates the I
previous byte transmitted on the I
example, in receive mode if firmware sets the Continue bit and
clears the ACK bit.
Bit 0: I
Set this bit to override GPIO definition with I
function on the two I
these pins are free to function as GPIOs. In I
mode, the two pins operate in open drain mode, independent of
the GPIO configuration setting.
2
C compatible bus. Writing a 1 to this bit generates an ACK
2
C Enable
2
C target address for the restart must be written
2
CY7C66013C, CY7C66113C
C transaction by not acknowledging the
2
C compatible pins. When this bit is cleared,
2
2
C compatible block during the first byte of
C compatible bus at the ACK bit time.
2
C start or restart. The Addr
2
C compatible bus. For
2
2
Page 24 of 59
C compatible
C compatible
2
C restart
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