CY7C66113C-LFXCT Cypress Semiconductor Corp, CY7C66113C-LFXCT Datasheet - Page 58

• Manufacturer Part Number: CY7C66113C-LFXCT
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good thermal
bond to the circuit board. A Copper (Cu) fill is to be designed into
the PCB as a thermal pad under the package. Heat is transferred
from the FX1 through the device’s metal paddle on the bottom
side of the package. Heat from here, is conducted to the PCB at
the thermal pad. It is then conducted from the thermal pad to the
PCB inner ground plane by a 5 x 5 array of via. A via is a plated
through hole in the PCB with a finished diameter of 13 mil. The
QFN’s metal die paddle must be soldered to the PCB’s thermal
pad. Solder mask is placed on the board top side over each via
to resist solder flow into the via. The mask on the top side also
minimizes outgassing during the solder reflow process.
Document Number: 38-08024 Rev. *D
Via hole for thermally connecting the
QFN to the circuit board ground plane.
Figure 57. Cross Section of the Area Underneath the QFN Package
PCB Material
Figure 58. Plot of the Solder Mask (White Area)
Cu Fill
Solder Mask
0.013” dia
0.017” dia
For further information on this package design please refer to the
application note Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology. This application note can
be downloaded from AMKOR’s website from the following URL
http://www.amkor.com/products/notes_papers/MLF_AppNote_
0902.pdf. The application note provides detailed information on
board mounting guidelines, soldering flow, rework process, etc.
Figure 29
package. The cross section is of only one via. The thickness of
the solder paste template should be 5 mil. It is recommended
that “No Clean” type 3 solder paste is used for mounting the part.
Nitrogen purge is recommended during reflow.
Figure 58
thermally connected and is not electrically connected inside the
chip. To minimize EMI, this pad should be connected to the
ground plane of the circuit board.
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
Cu Fill
is a plot of the solder mask pattern. This pad is
displays a cross sectional area underneath the
PCB Material
CY7C66013C, CY7C66113C
Page 58 of 59
[+] Feedback