CY7C66113C-LFXCT Cypress Semiconductor Corp, CY7C66113C-LFXCT Datasheet - Page 33

• Manufacturer Part Number: CY7C66113C-LFXCT
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Hub Ports Speed
Bit [0..3]: Port x Speed (where x = 1..4)
Set to 1 if the device plugged in to Port x is Low speed; Set to 0
if the device plugged in to Port x is Full speed.
Enabling and Disabling a USB Device
After a USB device connection is detected, firmware must
update status change bits in the hub status change data
structure that is polled periodically by the USB host. The host
responds by sending a packet that instructs the hub to reset and
enable the downstream port. Firmware then sets the bit in the
Hub Ports Enable register,
The hub repeater hardware responds to an enable bit in the Hub
Ports Enable register by enabling the downstream port, so that
USB traffic flows to and from that port.
If a port is marked enabled and is not suspended, it receives all
USB traffic from the upstream port, and USB traffic from the
downstream port is passed to the upstream port (unless babble
Hub Ports Enable Register
Bit [0..3]: Port x Enable (where x = 1..4)
Set to 1 if Port x is enabled; Set to 0 if Port x is disabled.
Bit [7..4]: Reserved.
The Hub Ports Enable register is cleared to zero by reset or bus
reset to disable all downstream ports as the default condition. A
port is also disabled by internal hub hardware (enable bit
Document Number: 38-08024 Rev. *D
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
7
Reserved
0
R/W
7
Reserved
R/W
0
Figure
6
Reserved
R/W
0
6
0
Reserved
R/W
35, for the downstream port.
5
Reserved
R/W
0
5
Reserved
0
R/W
Figure 35. Hub Ports Enable Register
Figure 34. Hub Ports Speed
4
Reserved
R/W
0
4
Reserved
R/W
0
Bit [7..4]: Reserved.
The Hub Ports Speed register is cleared to zero by reset or bus
reset. This must be set by the firmware on issuing a port reset.
The Reserved bits [7..4] should always read as ‘0.’
is detected). Low speed ports do not receive full speed traffic
from the upstream port.
When firmware writes to the Hub Ports Enable register to enable
a port, the port is not enabled until the end of any packet currently
being transmitted. If there is no USB traffic, the port is enabled
immediately.
When a USB device disconnection is detected, firmware must
update status bits in the hub change status data structure that is
polled periodically by the USB host. In suspend, a connect or
disconnect event generates an interrupt (if the hub interrupt is
enabled) even if the port is disabled.
cleared) if babble is detected on that downstream port. Babble is
defined as:
■
■
Any non idle downstream traffic on an enabled downstream
port at EOF2
Any downstream port with upstream connectivity established
at EOF2 (that is, no EOP received by EOF2).
3
Port 4 Speed Port 3 Speed Port 2 Speed Port 1 Speed
R/W
0
3
Port 4
Enable
R/W
0
CY7C66013C, CY7C66113C
2
R/W
0
2
Port 3
Enable
R/W
0
1
R/W
0
1
Port 2
Enable
R/W
0
ADDRESS 0x4A
ADDRESS 0x49
0
0
Page 33 of 59
R/W
0
Port 1
Enable
R/W
0
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