STPCI2GDYI STMicroelectronics, STPCI2GDYI Datasheet - Page 16

• Manufacturer Part Number: STPCI2GDYI
• Description: IC SYSTEM-ON-CHIP X86 516-PBGA
• Manufacturer: STMicroelectronics

Specifications of STPCI2GDYI

• Applications: Graphics Controller
• Core Processor: x86
• Controller Series: STPC® Atlas
• Interface: UART
• Number Of I /o: 16
• Voltage - Supply: 2.45 V ~ 2.7 V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant

STPC® ATLAS
Table 2-2. Definition of Signal Pins
16/108
1
CS#[1:0]
CS#[3]/MA[12]/BA[1]
CS#[2]/MA[11]
MA[10:0]
BA[0]
RAS#[1:0]
CAS#[1:0]
MWE#
MD[0]
MD[53:1]
MD[63:54]
DQM[7:0]
PCI INTERFACE
AD[31:0]
CBE[3:0]
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
PAR
PERR#
SERR#
LOCK#
PCI_REQ#[2:0]
PCI_GNT#[2:0]
PCI_INT#[3:0]
ISA BUS INTERFACE
LA[23:17]
SA[19:0]
SD[15:0]
IOCHRDY
ALE
BHE#
MEMR#, MEMW#
SMEMR#, SMEMW#
IOR#, IOW#
MASTER#
MCS16#
IOCS16#
REF#
AEN
IOCHCK#
RTCRW#
Note
Signal Name
1
; See
Table 2-3
for buffer type descriptions
Dir
I/O BD8STRUP_FT
I/O BD8TRP_TC
I/O BD8STRUP_FT
I/O BD8PCIARP_FT
I/O BD8PCIARP_FT
I/O BD8PCIARP_FT
I/O BD8PCIARP_FT
I/O BD8PCIARP_FT
I/O BD8PCIARP_FT
I/O BD8PCIARP_FT
I/O BD8PCIARP_FT
I/O BD8PCIARP_FT
I/O BD8STRP_FT
I/O BD8STRUP_FT
I/O BD8STRUP_FT
O BD8STRP_TC
O BD16STARUQP_TC
O BD16STARUQP_TC
O BD16STARUQP_TC Memory Row & Column Address
O BD16STARUQP_TC Bank Address
O BD16STARUQP_TC Row Address Strobe
O BD16STARUQP_TC Column Address Strobe
O BD16STARUQP_TC Write Enable
O BD8STRP_TC
O BD8PCIARP_FT
O BD8PCIARP_FT
O BD8STRUP_FT
O BD8STRUP_FT
O BD4STRP_FT
O BD8STRUP_FT
O BD8STRUP_FT
O BD4STRP_FT
O BD8STRP_FT
I
I
I
I
I
I
I
I
I
TLCHT_FT
BD8PCIARP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRUP_FT
BD4STRUP_FT
BD4STRUP_FT
BD8STRP_FT
BD4STRUP_FT
Buffer Type
1
DIMM Chip Select
DIMM Chip Select
Memory Address
Bank Address
DIMM Chip Select
Memory Address
Memory Data
Memory Data
Memory Data
Data Input/Ouput Mask
Address / Data
Bus Commands / Byte Enables
Cycle Frame
Target Ready
Initiator Ready
Stop Transaction
Device Select
Parity Signal Transactions
System Error
PCI Lock
PCI Request
PCI Grant
PCI Interrupt Request
Unlatched Address Bus
Latched Address Bus
Data Bus
I/O Channel Ready
Address Latch Enable
System Bus High Enable
Memory Read & Write
System Memory Read and Write
I/O Read and Write
Add On Card Owns Bus
Memory Chip Select 16
I/O Chip Select 16
Refresh Cycle
Address Enable
I/O Channel Check (ISA)
RTC Read / Write#
Parity Error
Description
Qty
11
53
10
32
20
16
2
1
1
1
2
2
1
8
4
1
1
1
1
1
1
1
1
1
3
3
4
1
1
7
1
1
1
2
2
2
1
1
1
1
1
1