STPCI2GDYI STMicroelectronics, STPCI2GDYI Datasheet - Page 50

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STPCI2GDYI

Manufacturer Part Number
STPCI2GDYI
Description
IC SYSTEM-ON-CHIP X86 516-PBGA
Manufacturer
STMicroelectronics
Datasheet

Specifications of STPCI2GDYI

Applications
Graphics Controller
Core Processor
x86
Controller Series
STPC® Atlas
Interface
UART
Number Of I /o
16
Voltage - Supply
2.45 V ~ 2.7 V
Operating Temperature
-40°C ~ 115°C
Mounting Type
Surface Mount
Package / Case
516-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant

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STPC® ATLAS
4.5.2 RESET SEQUENCE
Figure 4-4
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
Figure 4-4. Reset timing diagram
50/108
1
14 MHz
SYSRSTI#
ISACLK
Strap Options
HCLK
PCI_CLK
SYSRSTO#
describes the reset sequence of the
MD[63:0]
1.6 V
VALID CONFIGURATION
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
2.3 ms

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