STPCI2GDYI STMicroelectronics, STPCI2GDYI Datasheet - Page 75

• Manufacturer Part Number: STPCI2GDYI
• Description: IC SYSTEM-ON-CHIP X86 516-PBGA
• Manufacturer: STMicroelectronics

Specifications of STPCI2GDYI

• Applications: Graphics Controller
• Core Processor: x86
• Controller Series: STPC® Atlas
• Interface: UART
• Number Of I /o: 16
• Voltage - Supply: 2.45 V ~ 2.7 V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant

6.2. STPC CONFIGURATION
The STPC is a very flexible product thanks to
decoupled clock domains and to strap options
enabling a user-optimized configuration.
As some trade off are often necessary, it is
important to do an analysis of the application
needs prior to design a system based on this
product. The applicative constraints are usually
the following:
Some other elements can help to tune the choice:
On the STPC side, the configurable parameters
are the following:
6.2.1. LOCAL BUS / ISA BUS
The selection between the ISA bus and the Local
Bus is relatively simple. The first one is a standard
bus but slow. The Local Bus is fast and
programmable but doesn't support any DMA nor
external master mechanisms. The
below summarize the selection:
Table 6-1. Bus mode selection
Before implementing a function requiring DMA
capability on the ISA bus, it is recommended to
check if it exists on PCI, or if it can be implemented
differently, in order to use the local bus mode.
6.2.2. CLOCK CONFIGURATION
The CPU clock and the memory clock are
independent unless the "synchronous mode" strap
option is set (see the STRAP OPTIONS chapter).
The potential clock configurations are then
Legacy I/O device (Floppy, ...), Super I/O
DMA capability (Soundblaster)
Flash, SRAM, basic I/O device
Fast boot
Boot flash of 4MB or more
Programmable Chip Select
- CPU performance
- graphics / video performances
- power consumption
- PCI bandwidth
- booting time
- EMC
- Code size of CPU Consuming tasks
- Data size and location
- Synchronous / asynchronous mode
- HCLK speed
- MCLK speed
- Local Bus / ISA bus
Need
Table 6-1
Selection
Local Bus
Local Bus
Local Bus
Local Bus
ISA Bus
ISA Bus
Table 6-2. Main STPC modes
The
compared to the asynchronous mode is a lower
latency when accessing SDRAM from the CPU or
the PCI (saves 4 MCLK cycles for the first access
of the burst). For the same CPU to Memory
transfer performance, MCLK has to be roughly
higher by 20MHz between SYNC and ASYNC
modes to get the same system performance level
(example: 66MHz SYNC = 86MHz ASYNC) .
In all cases, use SDRAM with CAS Latency equals
to 2 (CL2) for the best performances.
The advantage of the asynchronous mode is the
capability to reprogram the MCLK speed on the fly.
This could help for applications where power
consumption must be optimized.
The last, and more complex, information to
consider is the behaviour of the software. In case
high CPU or FPU computation is needed, it is
sometime better to be in DX2-133/MCLK=66
synchronous
asynchronous mode. This depends on the locality
of the number crunching code and the amount of
data manipulated.
The
right column correspond to the configuration
number as described in
Table 6-3. Clock mode selection
Obviously, the values for HCLK or MCLK can be
reduced compared to
need to push the device at its limits, or when
avoiding to use specific frequency ranges (FM
radio band for example).
6.3. ARCHITECTURE RECOMMENDATIONS
This
implementations for the STPC interfaces. For
more
Schematics from the STPC web site.
Need CPU power
Critical code fits into L1 cache
Need CPU power
Code or data does not fit into L1 cache
Need flexible SDRAM speed
C
1
2
Table 6-3
Asynchronous
Synchronous
advantage
section
details,
Mode
mode
below gives some examples. The
Constraints
describes
of
download
HCLK
Table 6-2
MHz
66
66
than
the
Table 6-2
synchronous
clock ratio
CPU clock
DX2-133/MCLK=90
133 (x2)
133 (x2)
the
in case there is no
STPC® ATLAS
the
:
recommend
Reference
MCLK
MHz
75/108
66
90
mode
C
1
3
2
1