MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 72

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Design Information
The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down
sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.
5.1.1
If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads
will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance
state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must
power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4
V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times
on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection
clamp diodes.
The recommended power up sequence is as follows:
Use one microsecond or slower rise time for all supplies.
72
Note:
1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than
2. It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM
3. Input voltage must not be greater than the supply voltage (VDD_IO, VDD_IO_MEM,
4. Use 1 microsecond or slower rise time for all supplies.
3.3V
2.5V
1.5V
0
0.4 V at any time, including power-up.
up to 0.9 V then separate for completion of ramps.
VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time, including during power-up.
Power Up Sequence
1
2
Figure 52. Supply Voltage Sequencing
MPC5200 Data Sheet, Rev. 4
VDD_IO,
VDD_IO_MEM (SDR)
VDD_IO_MEM (DDR)
VDD_CORE,
PLL_AVDD
Freescale Semiconductor
Time