MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 76

IC MPU 32BIT 400MHZ 272-PBGA

MPC5200CVR400B

Manufacturer Part Number
MPC5200CVR400B
Description
IC MPU 32BIT 400MHZ 272-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC5200CVR400B

Processor Type
MPC52xx PowerPC 32-Bit
Speed
400MHz
Voltage
1.5V
Mounting Type
Surface Mount
Package / Case
272-PBGA
Processor Series
MPC52xx
Core
e300
Development Tools By Supplier
MEDIA5200KIT1E
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
2.5 V, 3.3 V
Minimum Operating Temperature
- 40 C
Core Size
32 Bit
No. Of I/o's
56
Ram Memory Size
16KB
Cpu Speed
400MHz
No. Of Timers
8
Embedded Interface Type
CAN, I2C, SCI, SPI
No. Of Pwm Channels
8
Digital Ic Case Style
TEPBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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System Design Information
For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and
which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended.
To reset the MPC5200 via the COP connector, the HRESET pin of the COP should be connected to the
HRESET pin of the MPC5200. The circuitry shown in
JTAG_TRST separately, while any other board sources can drive PORRESET.
76
NOTES:
1
2
3
4
Pin #
BDM
With respect to the emulator tool’s perspective:
Input is really an output from the embedded G2_LE core.
Output is really an input to the core.
From the board under test, power sense for chip power.
HALTED is not available from G2_LE core.
Input to the G2_LE core to enable/disable soft-stop condition during breakpoints. MPC5200
internal ties core_qack_ to GND in its normal/functional mode (always asserted).
8
7
6
5
4
3
2
1
See Note
See Note
JTAG_TRST
JTAG_TDO
JTAG_TCK
JTAG_TDI
MPC5200
I/O Pin
Table 53. COP/BDM Interface Signals (continued)
3
4
.
.
Connector
MPC5200 Data Sheet, Rev. 4
halted
VDD
qack
BDM
N/C
trst
tdo
tck
tdi
2
4
3
PullUp/Down
100k Pull-Up
100k Pull-Up
100k Pull-Up
Figure 55
Internal
allows the COP to assert HRESET or
PullUp/Down
10k Pull-Up
10k Pull-Up
10k Pull-Up
External
Freescale Semiconductor
I/O
O
O
O
O
I
I
1

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