MPC8560PX833LB Freescale Semiconductor, MPC8560PX833LB Datasheet - Page 35

• Manufacturer Part Number: MPC8560PX833LB
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8560PX833LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Table 32
bypassed.
Freescale Semiconductor
Local bus clock to output high impedance
for LAD/LDP
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4. All signals are measured from OV
5. Input timings are measured at the pin.
6. The value of t
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
8. Guaranteed by characterization.
9. Guaranteed by design.
Local bus cycle time
Internal launch/capture clock to LCLK delay
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1). Also, t
the output (O) going invalid (X) or output hold time.
complementary signals at OV
question for 3.3-V signaling levels.
bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
through the component pin is less than or equal to the leakage current specification.
describes the general timing parameters of the local bus interface of the MPC8560 with the DLL
LBOTOT
Parameter
Parameter
(First two letters of functional block)(reference)(state)(signal)(state)
Table 31. Local Bus General Timing Parameters—DLL Enabled (continued)
LBKHOX
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
Table 32. Local Bus General Timing Parameters—DLL Bypassed
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
symbolizes local bus timing (LB) for the t
DD
/2.
DD
/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OV
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
POR Configuration
POR Configuration
(default)
(default)
—
—
—
—
—
—
—
—
for outputs. For example, t
LBK
Symbol
Symbol
t
t
t
(First two letters of functional block)(signal)(state) (reference)(state)
LBKSKEW
t
t
t
t
t
t
LBKHOZ2
LBKLOV1
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBK
LBKHKT
LBOTOT
t
clock reference (K) to go high (H), with respect to
LBK
clock reference (K) goes high (H), in this case for
1
1
Min
-1.8
-1.3
Min
6.0
2.3
5.7
5.6
1.5
—
—
—
LBIXKH1
Max
Max
150
-0.3
3.9
1.2
2.5
3.8
—
—
—
—
—
—
DD
symbolizes local bus
of the signal in
Unit
Unit
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
Local Bus
Notes
Notes
3, 9
4, 5
4, 5
4, 5
4, 5
7, 9
2
8
6
4
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