MPC8560PX833LB Freescale Semiconductor, MPC8560PX833LB Datasheet - Page 54

• Manufacturer Part Number: MPC8560PX833LB
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8560PX833LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

PCI/PCI-X
54
SYSCLK to output high impedance
Input setup to SYSCLK
Input hold from SYSCLK
REQ64 to HRESET
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
4. Input timings are measured at the pin.
5. The timing parameter t
6. The setup and hold time is with respect to the rising edge of HRESET.
7. The timing parameter t
8. The reset assertion timing requirement for HRESET is 100 μs.
9. Guaranteed by characterization.
10.Guaranteed by design.
block)(signal)(state) (reference)(state)
example, t
(V) relative to the SYSCLK clock, t
symbolizes PCI/PCI-X timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal
(F) going to the valid (V) state.
delivered through the component pin is less than or equal to the leakage current specification.
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
see
Bus Specifications.
Section 15,
PCIVKH
“Clocking.”
symbolizes PCI/PCI-X timing (PC) with respect to the time the input signals (I) reach the valid state
Parameter
9
Table 43. PCI AC Timing Specifications at 66 MHz (continued)
setup time
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
PCRHFV
SYS
indicates the minimum and maximum CLK cycle times for the various specified
for inputs and t
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
SYS
, reference (K) going to the high (H) state or setup time. Also, t
(first two letters of functional block)(reference)(state)(signal)(state)
Symbol
t
t
t
t
t
t
PCRHRX
PCKHOZ
PCRVRH
PCRHFV
PCIVKH
PCIXKH
1
10 × t
Min
3.0
—
10
0
0
SYS
(first two letters of functional
Max
14
50
—
—
—
—
Freescale Semiconductor
clocks
clocks
Unit
ns
ns
ns
ns
for outputs. For
PCRHFV
2, 3, 10
5, 6, 10
Notes
2, 4, 9
2, 4, 9
6, 10
7, 10