MPC8360EVVAJDGA Freescale Semiconductor, MPC8360EVVAJDGA Datasheet - Page 6
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MPC8360EVVAJDGA
Manufacturer Part Number
MPC8360EVVAJDGA
Description
IC MPU POWERQUICC II PRO 740TBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Specifications of MPC8360EVVAJDGA
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
533MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
740-TBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8360E-RDK
Maximum Clock Frequency
533 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
533MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
TBGA
No. Of Pins
740
Rohs Compliant
Yes
For Use With
MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8360EVVAJDGA
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MPC8360EVVAJDGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8360EVVAJDGA
Manufacturer:
FREESCALE
Quantity:
20 000
Overview
6
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
•
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key
— ARC four execution unit (AFEU)
— Message digest execution unit (MDEU)
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
— Storage/NAS XOR parity generation accelerator for RAID applications
Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory
controller on the MPC8358E
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus;
— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports
— Full ECC support (when the MPC8360E is configured as 2×32-bit DDR memory controllers,
— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
— External driver impedance calibration
— On-die termination (ODT)
– ECB, CBC, CCM, and counter modes
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either SHA or MD5 algorithm
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
on the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus
MPC8358E) data rate
both support ECC)
pages for DDR2)
Freescale Semiconductor