MPC8360EVVAJDGA Freescale Semiconductor, MPC8360EVVAJDGA Datasheet - Page 63

• Manufacturer Part Number: MPC8360EVVAJDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVAJDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 533 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 46
Figure 47
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 47
Freescale Semiconductor
UTOPIA inputs—Internal clock input setup time
UTOPIA inputs—External clock input setup time
UTOPIA inputs—Internal clock input hold time
UTOPIA inputs—External clock input hold time
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
2. The symbols used for timing specifications follow the pattern of t
3. In rev. 2.0 silicon, due to errata, t
are measured at the pin.
inputs and t
outputs internal timing (UI) for the time t
invalid (X).
Errata QE_UPC3 in Chip Errata for the MPC8360E, Rev. 1 .
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
UtopiaCLK (Input)
provides the AC test load for the UTOPIA.
and
shows the UTOPIA timing with external clock.
Output Signals:
Input Signals:
(first two letters of functional block)(reference)(state)(signal)(state)
Figure 48
UTOPIA
UTOPIA
Characteristic
Output
Table 60. UTOPIA AC Timing Specifications
represent the AC timing from
Figure 47. UTOPIA AC Timing (External Clock) Diagram
t
UEIVKH
UEIVKH
UTOPIA
minimum is 4.3 ns and t
Figure 46. UTOPIA AC Test Load
Z
memory clock reference (K) goes from the high state (H) until outputs (O) are
0
= 50 Ω
t
UEKHOX
t
UEKHOV
t
UEIXKH
UEIXKH
Table
(first two letters of functional block)(signal)(state)(reference)(state)
Symbol
for outputs. For example, t
t
t
t
t
UEIVKH
UEIXKH
UIIVKH
UIIXKH
minimum is 1.4 ns under specific conditions. Refer to
56. Note that although the specifications
2
R
L
= 50 Ω
1
(continued)
Min
2.4
6
4
1
OV
UIKHOX
DD
/2
Max
—
—
—
—
symbolizes the UTOPIA
Unit
ns
ns
ns
ns
UTOPIA/POS
Notes
for
—
—
3
3
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