GCIXP1240AB Intel, GCIXP1240AB Datasheet - Page 129
GCIXP1240AB
Manufacturer Part Number
GCIXP1240AB
Description
IC MPU NETWORK 200MHZ 432-BGA
Manufacturer
Intel
Specifications of GCIXP1240AB
Rohs Status
RoHS non-compliant
Processor Type
Network
Features
32-bit StrongARM RISC Core
Speed
200MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
432-BGA
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Other names
837151
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4.3.8.4
4.3.8.5
Datasheet
Figure 68. BootROM Read
SRAM Bus - BootROM and SlowPort Timings
Timing for the BootROM and SlowPort areas are programmable through the SRAM configuration
registers described in the IXP1200 Network Processor Family Microcode Programmer’s Reference
Manual. The designer should refer to this manual to understand restrictions in selecting timing
values. Each timing illustration shows the appropriate register settings to generate the timing
shown.
SRAM Bus - BootRom Signal Protocol and Timing
Boot ROM Chip select signal
Externally Generated Signal
SLOW_EN_L & CE_L<3:0>
Example for the following setting in SRAM registers
SRAM_SLOW_CONFIG
SRAM_BOOT_CONFIG
31:24
09
31:16
Cycle Count =
SLOW_EN_L
RES
LOW_EN_L
CH_L<3:0>
23:16
DQ<31:0>
05
SLOW_RD_L/SLOW_WE_L Assert. (9)
A<18:0>
MRD_L
FWE_L
SCLK
SLOW_RD_L/SLOW_WE_L Deassert. (5)
15:8
15:8
0x0B
0A
2
SLOW__EN_L Assert (10)
1
0x0B
7:0
7:0
03
BootROM Cycle Count (11)
Cycle time = Cycle Count + 1 (12 cycles)
SLOW__EN_L Deassert. (3)
0
SRAM SlowPort Cycle Count (Does not apply to BootROM)
11
BootROM Cycle Count (11)
10
SLOW_EN_L Assert. (10)
9
SLOW_RD_L Assert. (9)
8
7
Valid CE
Valid Address
6
Intel
Valid
Valid CE
5
®
IXP1240 Network Processor
4
SLOW_RD_L Deassert. (5)
3
SLOW_EN_L Deassert. (3)
2
1
0
11
A8615-01
10
9
129
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