GCIXP1240AB Intel, GCIXP1240AB Datasheet - Page 18
GCIXP1240AB
Manufacturer Part Number
GCIXP1240AB
Description
IC MPU NETWORK 200MHZ 432-BGA
Manufacturer
Intel
Specifications of GCIXP1240AB
Rohs Status
RoHS non-compliant
Processor Type
Network
Features
32-bit StrongARM RISC Core
Speed
200MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
432-BGA
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Other names
837151
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2.5.4
2.5.5
18
Table 6.
®
IXP1240 Network Processor
SDRAM Configurations
SDRAM Configurations
SRAM Unit
The IXP1240 provides an SRAM Unit for very high bandwidth memory for storage of lookup
tables and other data for the packet processing Microengines. The SRAM Unit controls the SRAM
(up to 8 Mbytes), BootROM (up to 8 Mbytes) for booting, and 2 Mbytes of SlowPort address space
for peripheral device access. The I/O signal timing is determined by internal address decodes and
configuration registers for the BootROM and SlowPort address regions. The SRAM Unit includes
an 8 entry Push/Pop register list for fast queue operations, bit test, set and clear instructions for
atomic bit operations, and an 8 entry CAM for Read Locks.
The SRAM interface operates at one-half the IXP1240 core frequency (0.5 * F
The SRAM Unit supports both Pipelined Burst Double Cycle Deselect (DCD) and Flowthru
SRAM types. Other SSRAM devices, including single cycle deselect, are not supported. The bus is
also used to attach BootROM and can be used to interface other peripheral devices such as custom
interface logic or MAC management ports. The SRAM interface provides three separate timing
domains for the three device types: SRAM, BootROM, and Peripheral (also referred to as SlowPort
access).
BootROM devices may be either 32 bits or 16 bits in width. This is determined by GPIO[3] during
reset. When 16-bit BootROM devices are used, the maximum BootROM address space is reduced
from 8 Mbytes to 4 Mbytes.
Figure 4
128 Mbytes
128 Mbytes
256 Mbytes
16 Mbytes
32 Mbytes
64 Mbytes
32 Mbytes
64 Mbytes
64 Mbytes
8 Mbytes
Memory
Total
details the major components of the SRAM Unit.
Number of
Chips
4
8
4
8
4
8
4
8
4
8
128 Mbit
128 Mbit
256 Mbit
256 Mbit
16 Mbit
16 Mbit
64 Mbit
64 Mbit
64 Mbit
64 Mbit
DRAM
Size
Configuration
512 K x 16-bit
2 M x 16-bit
1 M x 16-bit
2 M x 16-bit
4 M x 16-bit
(per bank)
1 M x 8-bit
4 M x 8-bit
2 M x 8-bit
4 M x 8-bit
8 M x 8-bit
Internal
Banks
2
2
2
2
4
4
4
4
4
4
Bank Bits
1
1
1
2
2
2
2
1
2
2
RAS Bits
core
13
13
12
12
12
12
13
13
11
11
).
Datasheet
CAS Bits
10
10
8
9
8
9
8
9
9
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