668-0003-C Rabbit Semiconductor, 668-0003-C Datasheet - Page 119

• Manufacturer Part Number: 668-0003-C
• Description: IC CPU RABBIT2000 30MHZ 100PQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0003-C

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 2000 8-Bit
• Speed: 30MHz
• Voltage: 2.7V, 3V, 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Features: -
• Other names: 316-1004; 668-0003

place since the last read of the status register. When the status register is read, these bits
are cleared. No bit will be lost. Either it will be read by the status register read or it will be
set after the status register read is complete. If a bit is on and the corresponding interrupt is
enabled, an interrupt will occur when priorities allow. However, a separate interrupt is not
guaranteed for each bit with an enabled interrupt. If the bit is read in the status register, it
is cleared and no further interrupt corresponding to that bit will be requested. It is possible
that one bit will cause an interrupt, and then one or more additional bits will be set before
the status register is read. After these bits are cleared, they cannot cause an interrupt. If
any bits are on, and the corresponding interrupt is enabled, then the interrupt will take
place as soon as priorities allow. However, if the bit is cleared before the interrupt is
latched, the bit will not cause an interrupt. The proper rule to follow is for the interrupt
routine to handle all bits that it sees set.
11.1.1 Timer A I/O Registers
The I/O registers for Timer A are listed in Table 11-1.
The control/status register for Timer A (TACSR) is laid out as shown in Table 11-2.
Bits 1, 4–7—Read/write, terminal count reached on timers A1 and A4–A7. Reading this
status register clears any bits (bits 1 and 4–7) that are on. Writing to these bits enables the
interrupts for the corresponding timer.
Bit 0—Write, set to a "1" to enable the clock (perclk/2) for Timer A, set to "zero" to dis-
able the clock (perclk/2 in Figure 11-1). Bits 1 and 4–7 are written (write only) to enable
the interrupt for the corresponding timer.
Chapter 11 Timers
Read
Write
Timer A Control/Status Register
Timer A Control Register
Timer A1 Time Constant 1 Register
Timer A4 Time Constant 4 Register
Timer A5 Time Constant 5 Register
Timer A6 Time Constant 6 Register
Timer A7 Time Constant 7 Register
A7 count
done
A7 interrupt
enable
Bit 7
Table 11-2. Timer A Control and Status Register (adr = 0x0A0)
Register Name
A6 count
done
A6 interrupt
enable
Bit 6
Table 11-1. Timer A I/O Registers
A5 count
done
A5 interrupt
enable
Bit 5
TACSR
TACR
TAT1R
TAT4R
TAT5R
TAT6R
TAT7R
Register Mnemonic
A4 count
done
A4 interrupt
enable
Bit 4
0
x
Bit 3
0
x
Bit 2
A0
A4
A3
A9
AB
AD
AF
I/O address (hex)
A1 count
done
A1 interrupt
enable
Bit 1
This bit is
write only.
1—enable
Timer A
R/W
W
W
W
W
W
W
Bit 0
R/W
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