668-0003-C Rabbit Semiconductor, 668-0003-C Datasheet - Page 213
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668-0003-C
Manufacturer Part Number
668-0003-C
Description
IC CPU RABBIT2000 30MHZ 100PQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0003.pdf
(228 pages)
Specifications of 668-0003-C
Rohs Status
RoHS non-compliant
Processor Type
Rabbit 2000 8-Bit
Speed
30MHz
Voltage
2.7V, 3V, 3.3V, 5V
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Features
-
Other names
316-1004
668-0003
668-0003
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Part Number:
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B.2.3 Serial Port Changes
Two features were added to the Rabbit 2000 serial port hardware in revisions A–C to
improve and simplify asynchronous serial and clocked serial communication.
Asynchronous Serial Port
In the asynchronous transmission mode, serial data are transmitted in the following order.
In the original Rabbit 2000 it was difficult to transmit the additional stop bit. This could
only be done by inserting a time delay before the next byte was transmitted. An additional
register, the long stop register, was added in revisions A–C. The register serves as an alter-
nate data-out register, and data stored in this register will be transmitted with 2 stop bits
(high level at the Tx pin). This simplifies implementing “9th bit” protocols as well as
sending parity for compatibility with legacy systems. With the new register, data may be
conveniently transmitted with either a “1” or “0” bit inserted following the last data bit,
and that bit will then be followed by a stop bit.
Section 12.6 and Section 12.7 provide additional information about asynchronous serial
data transmission.
The Serial Port x Long Stop Register (SxLR) is only present in revisions A–C.
Appendix B Rabbit 2000 Revisions
7:0
Bit(s)
Serial Port x Long Stop Register
Read
Write
Table B-6. Asycnchronous Serial Data Transmission Order
Value
start bit
Start
Returns the contents of the receive buffer.
Loads the transmit buffer with an address byte, marked with a “one” address bit,
for transmission.
Table B-7. Long Stop Register, All Ports
7 or 8 data bits
Data Bits
Special Flag
Stop Bit or
address flag
parity bit
stop bit
stop bit
(SALR)
(SBLR)
(SCLR)
(SDLR)
Description
Stop Bit
stop bit
stop bit
stop bit
—
(Address = 0xC2)
(Address = 0xD2)
(Address = 0xE2)
(Address = 0xF2)
207
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