668-0003-C Rabbit Semiconductor, 668-0003-C Datasheet - Page 150

• Manufacturer Part Number: 668-0003-C
• Description: IC CPU RABBIT2000 30MHZ 100PQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0003-C

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 2000 8-Bit
• Speed: 30MHz
• Voltage: 2.7V, 3V, 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Features: -
• Other names: 316-1004; 668-0003

If the user for some reason wants to depart from the suggested protocols and poll a register
while waiting for the other side to write something to the register, the user should be aware
that all the bits might not change at the exact same time when the result changes, and a
transitional value could be read from the register where some bits have changed to the new
value and others have not. To avoid being confused by a transitional value, the user can
read the register twice and make sure both values are the same before accepting the value,
or the user can test only one bit for a change. The transitional value can only exist for one
read of the register, and each bit will have its old value change to the new value at some
point without wavering back and forth. The existence of a transitional value could be very
rare and has the potential to create a bug that happens often enough to be serious, but so
infrequently as to be difficult to diagnose. Thus, the user is cautioned to avoid this situa-
tion.
Table 13-2 describes the slave port control register.
The functionality of the bits is as follows:
144
0—obey SMODE
pins
1—ignore SMODE
pins
Bit 7—If set to "0," the cold-boot feature will be enabled. Normally this bit is set to a "1"
Bits 6,5—May be used to read the input pins SMODE, SMODE0.
Bits 3,2—Bit 3 enables the slave port when set to a "1," disabling parallel port A and various
Bits 1,0—This 2-bit field sets the priority of the slave port interrupt. The interrupt is disabled
Bit 7 w/o
after the cold boot is complete. The cold boot for the slave port is enabled automatically if
(SMODE1, SMODE0) lines are set to (0,1) after the reset ends. This features disables the
normal operation of the processor and causes commands to be accepted via the slave port
register SPD0R. These commands cause data to be stored in memory or I/O space. When
the master that is managing the cold boot has finished setting up memory and I/O space,
the (SMODE1, SMODE0) pins are changed to code (0,0), which causes execution to start
at address zero. Typically this will start execution of a secondary boot program. At some
point, bit 7 will be set to a "1" so that the SMODEx pins can be used as normal input pins.
other port lines. Bit 3 is automatically set to a "1" if a cold boot is done via the slave port.
If bit 3 is "0," then bit 2 controls whether parallel port A is an input (bit 2 = 0) or an output
(bit 2 = 1).
by (0,0).
Table 13-2. Slave Port Control Register (SPCR) (adr = 0x024)
Reads SMODE pins
smode1,smode0
Bits 6,5 R/O
x
Bit 4
00—disable slave port,
port A is a byte wide input
port
01—disable slave port,
port A is a byte wide
output port
1x—enable the slave port
Rabbit 2000 Microprocessor User’s Manual
Bit 3,2 w/o
00—no slave
interrupt
pp—enable slave
port interrupt
priority 1–3.
Bits 1,0 w/o