MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 336
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MC68EC000EI12
Manufacturer Part Number
MC68EC000EI12
Description
IC MPU 32BIT 12MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Series
68K - M680X0r
Specifications of MC68EC000EI12
Processor Type
M680x0 32-Bit
Speed
12MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Core Size
32 Bit
Cpu Speed
12MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C To +70°C
Filter Terminals
SMD
Rohs Compliant
Yes
Clock Frequency
12MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EC000EI12
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68EC000EI12R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Floating Point Instructions
FDBcc
Operation:
Assembler
Syntax:
Attributes:
Description: This instruction is a looping primitive of three parameters: a floating-point
Floating-Point Status Register:
5-34
condition, a counter (data register), and a 16-bit displacement. The instruction first tests
the condition to determine if the termination condition for the loop has been met, and if
so, execution continues with the next instruction in the instruction stream. If the
termination condition is not true, the low-order 16 bits of the counter register are
decremented by one. If the result is – 1, the count is exhausted, and execution
continues with the next instruction. If the result is not equal to – 1, execution continues
at the location specified by the current value of the program counter plus the sign-
extended 16-bit displacement. The value of the program counter used in the branch
address calculation is the address of the displacement word.
The conditional specifier cc selects any one of the 32 floating- point conditional tests
as described in 3.6.2 Conditional Testing.
Condition Codes:
Quotient Byte:
Exception Byte:
Accrued Exception Byte:
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Condition True
Else Dn – 1
FDBcc Dn, < label >
Unsized
Then No Operation
If Dn
Else Execute Next Instruction
Floating-Point Test Condition,
Then PC + d
Decrement, and Branch
– 1
Not affected.
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
NEX2
INEX1
The IOP bit is set if the BSUN bit is set in the exception
byte. No other bit is affected.
(MC6888X, MC68040)
Dn
n
PC
Set if the NAN condition code is set and the
condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
FDBcc
MOTOROLA
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