MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 507

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PMOVE
Operation:
Assembler
Syntax:
Attributes:
Description: The contents of the MC68851 register copies to the address specified by < ea
MOTOROLA
> , or the data at < ea > copies into the MC68851 register.
The instruction is a quad-word operation for CPU root pointer, supervisor root pointer,
and DMA root pointer registers. It is a long-word operation for the translation control
register and a word operation for the breakpoint acknowledge control, breakpoint
acknowledge data, access control, PMMU status, and PMMU cache status registers.
PMOVE is a byte operation for the current access level, valid access level, and stack
change control registers.
The following side effects occur when data is read into certain registers:
CPU Root Pointer—Causes the internal root pointer table to be searched for the
new value. If there is no matching value, an entry in the root pointer table is selected
for replacement, and all address translation cache entries associated with the
replaced entry are invalidated.
Supervisor Root Pointer—Causes all entries in the address translation cache that
were formed with the supervisor root pointer (even globally shared entries) to be
invalidated.
DMA Root Pointer—Causes all entries in the address translation cache that were
formed with the DMA root pointer (even globally shared entries) to be invalidated.
Translation Control Register—If data written to the translation control register
attempts to set the E-bit and the E-bit is currently clear, a consistency check is per-
formed on the IS, TIA, TIB, TIC, TID, and PS fields.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
Else TRAP
PMOVE < PMMU Register > , < ea >
PMOVE < ea > , < PMMU Register >
Size = (Byte, Word, Long, Double Long)
Then MC68851 Register
Or Source
Move PMMU Register
MC68851 Register
(MC68851)
Destination
Supervisor (Privileged) Instructions
PMOVE
6-53