MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 528

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Supervisor (Privileged) Instructions
PTEST
PMMU Status Register:
6-74
Bus Error (B)—Set if a bus error was received during a descriptor fetch, or if < level >
Either PTESTR or PTESTW must be specified. These two instructions differ in the set-
ting of the A-bit of the PMMU status register. For systems where access levels are not
in use, either PTESTR or PTESTW may be used. U and M bits in the translation table
are not modified by this instruction.
If there is a specified address register parameter, the physical address of the last suc-
cessfully fetched descriptor is loaded into the address register. A descriptor is success-
fully fetched if all portions of the descriptor can be read by the MC68851 without
abnormal termination of the bus cycle. If the DT field of the root pointer used indicates
page descriptor, the returned address is $0.
The PTEST instruction continues searching the translation tables until reaching the
requested level or until a condition occurs that makes further searching impossible (i.e.,
a DT field set to invalid, a limit violation, or a bus error from memory). The information
in the PMMU status register reflects the accumulated values.
Limit (L)—Set if the limit field of a long descriptor was exceeded; cleared otherwise.
Supervisor Violation (S)—Set if a long descriptor indicated supervisor-only access and
Access Level Violation (A)—If PTESTR was specified, set if the RAL field of a long
Write Protection (W)—Set if the WP-bit of a descriptor was set or if a WAL field of a
Invalid (I)—Set if a valid translation was not available; cleared otherwise.
Modified (M)—If the tested address is found in the address translation cache, set to the
= 0 and an entry was found in the address translation cache with its BERR bit set;
cleared otherwise.
the < fc > parameter did not have bit 2 set; cleared otherwise.
descriptor would deny access. If PTESTW was specified, set if a WAL or RAL field
of a long descriptor would deny access; cleared otherwise.
long descriptor would deny access; cleared otherwise.
value of the M-bit in the address translation cache. If the tested address is found
in the translation table, set if the M-bit of the page descriptor is set; cleared
otherwise.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Get Information About Logical Address
(MC68851)
PTEST
MOTOROLA