MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 492

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Supervisor (Privileged) Instructions
PFLUSH
PFLUSHA
PFLUSHS
Operation:
Assembler
Syntax:
Attributes:
Description: PFLUSHA invalidates all entries in the address translation cache.
6-38
PFLUSH invalidates a set of address translation cache entries whose function code
bits satisfy the relation: (address translation cache function code bits and mask) = (FC
and MASK) for all entries whose task alias matches the task alias currently active when
the instruction is executed. With an additional effective address argument, PFLUSH
invalidates a set of address translation cache entries whose function code satisfies the
relation above and whose effective address field matches the corresponding bits of the
evaluated effective address argument. In both of these cases, address translation
cache entries whose SG bit is set will not be invalidated unless the PFLUSHS is spec-
ified.
The function code for this operation may be specified as follows:
1. Immediate—The function code is four bits in the command word.
2. Data Register—The function code is in the lower four bits of the MC68020 data
3. Source Function Code (SFC) Register—The function code is in the CPU SFC
4. Destination Function Code (DFC) Register—The function code is in the CPU
register specified in the instruction.
register. Since the SFC of the MC68020 has only three implemented bits, only
function codes $0D$7 can be specified in this manner.
DFC register. Since the DFC of the MC68020 has only three implemented bits,
only function codes $0D$7 can be specified in this manner.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
Else TRAP
PFLUSHA
PFLUSH FC,MASK
PFLUSHS FC,MASK
PFLUSH FC,MASK, < ea >
PFLUSHS FC,MASK, < ea >
Unsigned
Then Address Translation Cache Entries For Destination Address
Are Invalidated
Invalidate Entries in the ATC
(MC68851)
PFLUSHA
PFLUSHS
PFLUSH
MOTOROLA