MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet
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MC68EC020AA25 Summary of contents
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MICROPROCESSORS Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described ...
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The M68020 User’s Manual describes the capabilities, operation, and programming of the MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32- bit, second-generation, enhanced embedded microprocessor. Throughout this manual, “MC68020/EC020” is used when information applies to both the MC68020 and ...
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SECTION 1: OVERVIEW TABLE OF CONTENTS Paragraph Number 1.1 Features .................................................................................................. 1-2 1.2 Programming Model ................................................................................ 1-4 1.3 Data Types and Addressing Modes Overview ........................................ 1-8 1.4 Instruction Set Overview ......................................................................... 1-10 1.5 Virtual Memory and Virtual Machine Concepts ...
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SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 3.12 Power Supply Connections ..................................................................... 3-7 3.13 Signal Summary...................................................................................... 3-8 4.1 On-Chip Cache Organization and Operation .......................................... 4-1 4.2 Cache Reset ........................................................................................... 4-3 4.3 Cache Control ......................................................................................... 4-3 4.3.1 Cache ...
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SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 5.5.2 Retry Operation ................................................................................... 5-56 5.5.3 Halt Operation...................................................................................... 5-60 5.5.4 Double Bus Fault ................................................................................. 5-60 5.6 Bus Synchronization................................................................................ 5-62 5.7 Bus Arbitration ......................................................................................... 5-62 5.7.1 MC68020 Bus Arbitration .................................................................... 5-63 ...
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SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number Coprocessor Interface Description 7.1 Introduction ............................................................................................. 7-1 7.1.1 Interface Features ............................................................................... 7-2 7.1.2 Concurrent Operation Support ............................................................ 7-2 7.1.3 Coprocessor Instruction Format .......................................................... 7-3 7.1.4 Coprocessor System Interface ............................................................ 7-4 ...
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SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 7.3.1 Response CIR ..................................................................................... 7-24 7.3.2 Control CIR .......................................................................................... 7-24 7.3.3 Save CIR ............................................................................................. 7-25 7.3.4 Restore CIR ......................................................................................... 7-25 7.3.5 Operation Word CIR ............................................................................ 7-25 7.3.6 Command CIR ..................................................................................... ...
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SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 7.5.2.3 Privilege Violations........................................................................... 7-55 7.5.2.4 cpTRAPcc Instruction Traps ............................................................ 7-55 7.5.2.5 Trace Exceptions ............................................................................. 7-55 7.5.2.6 Interrupts .......................................................................................... 7-56 7.5.2.7 Format Errors ................................................................................... 7-57 7.5.2.8 Address and Bus Errors................................................................... 7-57 ...
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SECTION 1: OVERVIEW TABLE OF CONTENTS (Concluded) Paragraph Number 9.4 Clock Driver............................................................................................. 9-10 9.5 Memory Interface .................................................................................... 9-11 9.6 Access Time Calculations ....................................................................... 9-12 9.7 Module Support ....................................................................................... 9-14 9.7.1 Module Descriptor................................................................................ 9-14 9.7.2 Module Stack Frame ........................................................................... 9-16 ...
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SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS Figure Number 1-1 MC68020/EC020 Block Diagram ..................................................................... 1-3 1-2 User Programming Model ................................................................................ 1-5 1-3 Supervisor Programming Model Supplement .................................................. 1-6 1-4 Status Register (SR) ........................................................................................ 1-7 1-5 Instruction Pipe ................................................................................................ 1-13 2-1 ...
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SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS (Continued) Figure Number 5-24 Write Cycle Flowchart ...................................................................................... 5-33 5-25 Read-Write-Read Cycles—32-Bit Port ............................................................. 5-34 5-26 Byte and Word Write Cycles—32-Bit Port ........................................................ 5-35 5-27 Long-Word Operand Write—8-Bit Port ............................................................ 5-36 5-28 Long-Word ...
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SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS (Continued) Figure Number 7-4 Coprocessor Address Map in MC68020/EC020 CPU Space .......................... 7-7 7-5 Coprocessor Interface Register Set Map ......................................................... 7-7 7-6 Coprocessor General Instruction Format (cpGEN) .......................................... 7-8 7-7 Coprocessor Interface Protocol ...
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SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS (Concluded) Figure Number 7-45 MC68020/EC020 Postinstruction Stack Frame................................................ 7-48 8-1 Concurrent Instruction Execution ..................................................................... 8-3 8-2 Instruction Execution for Instruction Timing Purposes ..................................... 8-3 8-3 Processor Activity for Example 1 ..................................................................... 8-5 8-4 ...
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SECTION 1: OVERVIEW Table Number 1-1 Addressing Modes ........................................................................................... 1-9 1-2 Instruction Set .................................................................................................. 1-11 2-1 Address Space Encodings ............................................................................... 2-4 3-1 Signal Index ..................................................................................................... 3-3 3-2 Signal Summary............................................................................................... 3-8 5-1 DSACK1/DSACK0 Encodings and Results .................................................... 5-5 5-2 SIZ1, ...
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SECTION 1: OVERVIEW LIST OF TABLES (Continued) Table Number 9-1 Data Bus Activity for Byte, Word, and Long-Word Ports .................................. 9-6 9-2 V and GND Pin Assignments—MC68EC020 PPGA (RP Suffix) ................. 9-10 CC 9-3 V and GND Pin Assignments—MC68EC020 ...
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MC68020/EC020 ACRONYM LIST BCD — Binary-Coded Decimal CAAR — Cache Address Register CACR — Cache Control Register CCR — Condition Code Register CIR — Coprocessor Interface Register CMOS — Complementary Metal Oxide Semiconductor CPU — Central Processing Unit CQFP — ...
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SECTION 1 INTRODUCTION The MC68020 is the first full 32-bit implementation of the M68000 family of microprocessors from Motorola. Using VLSI technology, the MC68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile ...
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FEATURES The main features of the MC68020/EC020 are as follows: • Object-Code Compatible with Earlier M68000 Microprocessors • Addressing Mode Extensions for Enhanced Support of High-Level Languages • New Bit Field Data Type Accelerates Bit-Oriented Applications—e.g., Video Graphics • ...
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SEQUENCER AND CONTROL CONTROL STORE CONTROL LOGIC ADDRESS INSTRUCTION BUS ADDRESS BUS * 32-BIT ADDRESS PADS ADDRESS BUS BUS CONTROLLER WRITE PENDING PREFETCH PENDING BUFFER BUFFER MICROBUS CONTROL LOGIC BUS CONTROL SIGNALS * 24-Bit for MC68EC020 Figure 1-1. MC68020/EC020 Block ...
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PROGRAMMING MODEL The programming model of the MC68020/EC020 consists of two groups of registers, the user model and the supervisor model, that correspond to the user and supervisor privilege levels, respectively. User programs executing at the user privilege level ...
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Figure 1-2. User Programming Model MOTOROLA M68020 USER’S MANUAL DATA REGISTERS ...
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Figure 1-3. Supervisor Programming Model Supplement (CCR) M68020 USER’S MANUAL 0 INTERRUPT STACK A7' (ISP) POINTER 0 MASTER STACK A7'' (MSP) POINTER 0 STATUS SR ...
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The SR (see Figure 1-4) stores the processor status. It contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The condition codes are extend (X), negative ...
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DATA TYPES AND ADDRESSING MODES OVERVIEW For detailed information on the data types and addressing modes supported by the MC68020/EC020, refer to M68000PM/AD, M68000 Family Programmer’s Reference Manual . The MC68020/EC020 supports seven basic data types: 1. Bits 2. ...
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Register Direct Data Address Register Indirect Address Address with Postincrement Address with Predecrement Address with Displacement Address Register Indirect with Index 8-Bit Displacement Base Displacement Memory Indirect Postindexed Preindexed PC Indirect with Displacement PC Indirect with Index 8-Bit Displacement Base ...
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INSTRUCTION SET OVERVIEW For detailed information on the MC68020/EC020 instruction set, refer to M68000PM/AD, M68000 Family Programmer’s Reference Manual . The instructions in the MC68020/EC020 instruction set are listed in Table 1-2. The instruction set has been tailored to ...
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Mnemonic Description ABCD Add Decimal with Extend ADD Add ADDA Add Address ADDI Add Immediate ADDQ Add Quick ADDX Add with Extend AND Logical AND ANDI Logical AND Immediate ASL, ASR Arithmetic Shift Left and Right Bcc Branch Conditionally BCHG ...
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Virtual Machine A typical use for a virtual machine system is the development of software, such as an operating system, for a new machine also under development and not yet available for programming use virtual machine system, ...
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SEQUENCER CONTROL UNIT EXECUTION UNIT The sequencer is either executing microinstructions or awaiting completion of accesses that are necessary to continue executing microcode. The bus controller is responsible for all bus activity. The sequencer controls the bus controller, instruction execution, ...
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SECTION 2 PROCESSING STATES This section describes the processing states of the MC68020/EC020. It describes the functions of the bits in the supervisor portion of the SR and the actions taken by the processor in response to exception conditions. Unless ...
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PRIVILEGE LEVELS The processor operates at one of two privilege levels: the user level or the supervisor level. The supervisor level has higher privileges than the user level. Not all processor or coprocessor instructions are permitted to execute at ...
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The value of the M-bit in the SR does not affect execution of privileged instructions; both master and interrupt modes are at the supervisor privilege level. Instructions that affect the M-bit are MOVE to SR, ANDI to SR, EORI to ...
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RTE instruction restores the SR and PC to the values saved on the supervisor stack. The processor then continues execution at the restored PC address ...
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EXCEPTION PROCESSING An exception is defined as a special condition that preempts normal processing. Both internal and external conditions can cause exceptions. External conditions that cause exceptions are interrupts from external devices, bus errors, coprocessor-detected errors, and reset. Instructions, ...
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Exception Stack Frame Exception processing saves the most volatile portion of the current processor context on the top of the supervisor stack. This context is organized in a format called the exception stack frame. This information always includes a ...
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SECTION 3 SIGNAL DESCRIPTION This section contains brief descriptions of the input and output signals in their functional groups, as shown in Figure 3-1. Each signal is explained in a brief paragraph with reference to other sections that contain more ...
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SIGNAL INDEX The input and output signals for the MC68020/EC020 are listed in Table 3-1. Both the names and mnemonics are shown along with brief signal descriptions. Signals that are implemented in the MC68020, but not in the MC68EC020, ...
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Signal Name Mnemonic Function Codes FC2–FC0 Address Bus MC68020 A31–A0 MC68EC020 A23–A0 Data Bus D31–D0 Size SIZ1, SIZ0 * External Cycle Start ECS * Operand Cycle Start OCS Read/Write R/ W Read-Modify-Write Cycle RMC Address Strobe Data Strobe DS * ...
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ASYNCHRONOUS BUS CONTROL SIGNALS The following signals control synchronous bus transfer operations for the MC68020/EC020. Note that OCS, ECS, and DBEN are implemented in MC68020 and not implemented in the MC68EC020. Operand Cycle Start (OCS, MC68020 only) This output ...
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Data Buffer Enable (DBEN, MC68020 only) This output signal is an enable signal for external data buffers. This signal may not be required in all systems. Refer to Section 5 Bus Operation for more information about the relationship of DBEN ...
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BUS ARBITRATION CONTROL SIGNALS The following signals are the bus arbitration control signals used to determine which device in a system is the bus master. Note that BGACK is implemented in the MC68020 and not implemented in the MC68EC020. ...
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Halt (HALT) The assertion of this bidirectional open-drain signal indicates that the processor should suspend bus activity or, when used with BERR , that the processor should retry the current cycle. Refer to Section 5 Bus Operation for a description ...
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SIGNAL SUMMARY Table 3-2 provides a summary of the characteristics of the signals discussed in this section. Signal names preceded by an asterisk (*) are implemented in the MC68020 and not implemented in the MC68EC020. Signal Function Function Codes ...
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SECTION 4 ON-CHIP CACHE MEMORY The MC68020/EC020 incorporates an on-chip cache memory as a means of improving performance. The cache is implemented as a CPU instruction cache and is used to store the instruction stream prefetch accesses from the main ...
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SELECT TAG REPLACE Figure 4-1. MC68020/EC020 On-Chip Cache Organization When an instruction fetch occurs, the cache (if enabled) is first checked to determine if the ...
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CACHE RESET During processor reset, the cache is cleared by resetting all of the valid bits. The E and F bits in the CACR are also cleared. 4.3 CACHE CONTROL Only the MC68020/EC020 cache control circuitry can directly access ...
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F—Freeze Cache The F-bit is set to freeze the instruction cache. When the F-bit is set and a cache miss occurs, the entry (or line) is not replaced. When the F-bit is clear, a cache miss causes the entry (or ...
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SECTION 5 BUS OPERATION This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. ...
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Figure 5-1 shows the relationship between the clock signal, a typical input, and its associated internal signal. Furthermore, for all inputs, the processor latches the level of the input during a sample window around the ...
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When initiating a bus cycle, the MC68020 asserts ECS in addition to A1–A0, SIZ1, SIZ0, FC2–FC0, and R/W . ECS can be used to initiate various timing sequences that are eventually qualified with AS. Qualification with AS may be required ...
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The processor places the data on the data bus one-half clock cycle after asserted in a write ...
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DATA TRANSFER MECHANISM The MC68020/EC020 architecture supports byte, word, and long-word operands allowing access to 8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled by DSACK1/DSACK0. Byte, word, and long-word operands can be located on ...
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LONG-WORD OPERAND Figure 5-3. Internal Operand Representation Figure 5-4 shows the required organization of data ports on the MC68020/EC020 bus for 8-, 16-, and 32-bit devices. The four bytes shown in Figure 5-4 are connected through the internal data ...
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The multiplexer takes the four bytes of the 32-bit bus and routes them to their required positions. For example, OP0 can be routed to D31–D24, as would be the normal case can be routed to any other byte ...
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Table 5-4 lists the bytes required on the data bus for read cycles. The entries shown as OP3, OP2, OP1, and OP0 are portions of the requested operand that are read or written during that bus cycle and are defined ...
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Table 5-5 lists the combinations of SIZ1, SIZ0, A1, and A0 and the corresponding pattern of the data transfer for write cycles from the internal multiplexer of the MC68020/EC020 to the external data bus. Table 5-5. MC68020/EC020 Internal to External ...
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Figure 5-5 shows the transfer (write long-word operand to a word port. In the first bus cycle, the MC68020/EC020 places the four operand bytes on the external bus. Since the address is long-word aligned in this example, the ...
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CLK A31– FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-6. Long-Word Operand Write ...
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Figure 5-7 shows a word write to an 8-bit bus port. Like the preceding example, this example requires two bus cycles. Each bus cycle transfers a single byte. SIZ1 and SIZ0 for the first cycle specify two bytes; for the ...
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CLK * A31– FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-8. Word ...
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Misaligned Operands Since operands may reside at any byte boundary, they may be misaligned. A byte operand is properly aligned at any address; a word operand is misaligned at an odd address; a long word is misaligned at an ...
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S0 S2 CLK A31– FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 BYTE WRITE * For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. ...
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LONG-WORD OPERAND (REGISTER) 31 OP0 OP1 D31 MSB XXX OP1 OP3 Figure 5-11. Misaligned Long-Word Operand Read Figures 5-12 and 5-13 show a word transfer (write odd address in word-organized memory. This example is similar to the one ...
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CLK * A31– FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-13. Misaligned ...
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WORD OPERAND (REGISTER) 15 OP2 D31 DATA BUS WORD MEMORY MSB XXX OP3 Figure 5-14. Misaligned Word Operand Read from Word Bus Example Figures 5-15 and 5-16 show an example of a long-word transfer (write odd address in ...
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CLK * A31– FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 * For the MC68EC020, A23–A2. ** This signal does not apply to the MC68EC020. Figure 5-16. Misaligned ...
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LONG-WORD OPERAND (REGISTER) OP0 OP1 D31 DATA BUS LONG-WORD MEMORY MSB UMB XXX XXX OP1 OP2 Figure 5-17. Misaligned Long-Word Operand Read 5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment The combination of operand size, operand alignment, and ...
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Table 5-6 demonstrates that the processor always prefetches instructions by reading a long word from a long-word address (A1 00), regardless of port size or alignment. When the required instruction begins at an odd-word boundary, the processor attempts ...
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Table 5-7. Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports Transfer Size SIZ1 SIZ0 Byte Word Bytes ...
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A0 A1 SIZ0 SIZ1 R/W Figure 5-18. Byte Enable Signal Generation for 16- and 32-Bit Ports MOTOROLA UUD = UPPER UPPER DATA (32-BIT PORT) UMD = UPPER MIDDLE DATA (32-BIT PORT) LMD = LOWER MIDDLE DATA (32-BIT PORT) LLD = ...
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Bus Operation The MC68020/EC020 bus is used in an asynchronous manner allowing external devices to operate at clock frequencies different from the MC68020/EC020 clock. Bus operation uses the handshake lines (AS, DS, DSACK0, DSACK1, BERR, and HALT) to control ...
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All timing parameters referred to are described in Section 10 Electrical Characteristics system asserts DSACK1/DSACK0 for the required window around the falling edge of state 2 and obeys the proper bus protocol ...
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Read Cycle During a read cycle, the processor receives data from a memory, coprocessor, or peripheral device. If the instruction specifies a long-word operation, the MC68020/EC020 attempts to read four bytes at once. For a word operation, it attempts ...
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PROCESSOR ADDRESS DEVICE 1) ASSERT ECS/OCS FOR ONE-HALF CLOCK * 2) SET R/W TO READ ** 3) DRIVE ADDRESS ON A31–A0 4) DRIVE FUNCTION CODE ON FC2–FC0 5) DRIVE SIZ1, SIZ0 (FOUR BYTES) 6) ASSERT AS 7) ASSERT DS * ...
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S0 S2 CLK * A31– FC2–FC0 SIZ1 WORD SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD READ * Figure 5-21. Byte and Word Read Cycles—32-Bit Port 5- ...
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CLK * A31– FC2–FC0 SIZ1 LONG WORD SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 BYTE READ For the MC68EC020, A23–A2. * This signal does not apply ...
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S0 S2 CLK * A31– FC2–FC0 SIZ1 LONG WORD SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD READ LONG-WORD OPERAND READ FROM 16-BIT PORT * For the MC68EC020, A23–A2. ...
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State 0 MC68020—The read cycle starts in state 0 (S0). The processor asserts ECS, indicating the beginning of an external cycle. If the cycle is the first external cycle of a read operation, OCS is asserted simultaneously. During S0, the ...
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State 4 MC68020/EC020—At the end of state 4 (S4), the processor latches the incoming data. State 5 MC68020—The processor negates AS, DS, and DBEN during state 5 (S5). It holds the address valid during S5 to provide address hold time ...
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Write Cycle During a write cycle, the processor transfers data to memory or a peripheral device. Figure 5- flowchart of a write cycle operation for a long-word transfer. Figures 5-25– 5-28 are write cycle timing diagrams in ...
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CLK A31– FC2–FC0 SIZ1 LONG WORD SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D0 BYTE READ * For the MC68EC020, A23–A2. ** This signal does not apply to the ...
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S0 S2 CLK * A31- FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD WRITE * For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. ...
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CLK * A31– FC2–FC0 SIZ1 LONG WORD SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 OP0 D23–D16 OP1 D15–D8 OP2 D7–D0 OP3 BYTE WRITE * For the MC68EC020, A23–A2. This ...
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S0 S2 CLK * A31– FC2–FC0 SIZ1 LONG WORD SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD WRITE LONG-WORD OPERAND WRITE TO 16-BIT PORT * For the MC68EC020, A23–A2. ...
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State 0 MC68020—The write cycle starts in S0. The processor negates ECS, indicating the beginning of an external cycle. If the cycle is the first external cycle of a write operation, OCS is asserted simultaneously. During S0, the processor places ...
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State 4 MC68020/EC020—The processor issues no new control signals during S4. State 5 MC68020—The processor negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/W , ...
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PROCESSOR LOCK BUS 1) ASSERT RMC ADDRESS DEVICE * 1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2) SET R/W TO READ 3) DRIVE ADDRESS ON A31– DRIVE FUNCTION CODES ON FC2–FC0 5) DRIVE SIZ1, SIZ0 6) ASSERT AS 7) ...
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CLK * A31– FC2–FC0 SIZ1 SIZ0 R/W RMC ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–8 OP3 D7–D0 BERR HALT BG * For the MC68EC020, A23–A2. ** This signal does ...
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State 0 MC68020—The processor asserts ECS and OCS indicate the beginning of an external operand cycle. The processor also asserts RMC identify a read- modify-write cycle. The processor places a valid address on A31–A0 ...
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State 5 MC68020—The processor negates AS, DS, and DBEN during S5. If more than one read cycle is required to read in the operand(s), S0–S5 are repeated for each read cycle. When the read cycle(s) are complete, the processor holds ...
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State 9 MC68020/EC020—The processor asserts DS during S9, indicating that the data on the data bus is stable. As long as at least one of the DSACK1/DSACK0 signals is recognized by the end of S8 (meeting the asynchronous input setup ...
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FUNCTION CODE BREAKPOINT ACKNOWLEDGE 31 ACCESS LEVEL ...
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The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 5.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are: 1. FC2–FC0 are set 111 for CPU address space. ...
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S0 S2 CLK * A31–A4 A3–A1 A0 FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D24–D31 D23–D16 D7–D0 IPL2–IPL0 ** IPEND READ CYCLE * For the MC68EC020, A23–A4. ** This signal does not apply ...
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AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector or autovector. Instead of placing a vector number on the data bus and asserting DSACK1/DSACK0, the device asserts AVEC to ...
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S0 CLK * A31–A4 A1–A3 A0 FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D0 IPL2–IPL0 AVEC READ CYCLE * For the MC68EC020, A23–A4. ** This signal does not apply to the MC68EC020. Figure ...
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Breakpoint Acknowledge Cycle The breakpoint acknowledge cycle is generated by the execution of a BKPT instruction. The breakpoint acknowledge cycle allows the external hardware to provide an instruction word directly into the instruction pipeline as the program executes. This ...
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S0 S2 CLK * A31–A20 A19–A16 A15–A2 A1–A0 FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D23–D16 D15–D8 D7–D0 BERR HALT READ CYCLE Figure 5-36. Breakpoint Acknowledge Cycle Timing MOTOROLA ...
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S0 S2 CLK * A31–A0 FC2–FC0 SIZ1–SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D0 BERR HALT READ WITH BERR ASSERTED * For the MC68EC020, A23–A0. ** This signal does not apply to the MC68EC020. Figure ...
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Coprocessor Communication Cycles The MC68020/EC020 coprocessor interface provides instruction-oriented communication between the processor and as many as eight coprocessors. Coprocessor accesses use the MC68020/EC020 bus protocol except that the address bus supplies access information rather than a 32-bit address. ...
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The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACK1/DSACK0 assertion as follows (case numbers refer to Table 5-8): Normal Termination: DSACK1/DSACK0 is asserted; BERR and HALT remain negated (case 1). Halt Termination: HALT is asserted ...
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Table 5-8 lists various combinations of control signal sequences and the resulting bus cycle terminations. To ensure predictable operation, BERR and HALT should be negated according to parameters #28 and #57 in Section 10 Electrical Characteristics. DSACK1/DSACK0, BERR, and HALT ...
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BERR is recognized during a bus cycle in any of the following cases: 1. DSACK1/DSACK0 and HALT are negated and BERR is asserted. 2. HALT and BERR are negated and DSACK1/DSACK0 is asserted. BERR is then asserted within one clock ...
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S0 S2 CLK * A31–A20 A19–A16 A15–A2 A1–A0 FC2–FC0 SIZ1 SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D24 D23–D16 D15–D8 D7–D0 BERR HALT READ CYCLE * For the MC68EC020, A23–A20. ** This signal does not ...
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S0 S2 CLK * A31–A0 FC2–FC0 SIZ1–SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D0 IPL2–IPL0 BERR HALT WRITE WITH BERR ASSERTED * For the MC68EC020, A23–A0. ** This signal does not apply to the MC68EC020. ...
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CLK * A31–A0 FC2–FC0 SIZ1–SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 D31–D0 BERR HALT WRITE CYCLE RETRY SIGNALED * For the MC68EC020, A23–A0. ** This signal does not apply to the MC68EC020. MOTOROLA S4 ...
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Halt Operation When HALT is asserted and BERR is not asserted, the MC68020/EC020 halts external bus activity at the next bus cycle boundary. HALT by itself does not terminate a bus cycle. Negating and reasserting HALT in accordance with ...
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S0 S2 CLK * A31–A0 FC2–FC0 SIZ1–SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D0 BERR HALT READ * For the MC68EC020, A23–A0. ** This signal does not apply to the MC68EC020. Figure 5-41. Halt Operation ...
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BUS SYNCHRONIZATION The MC68020/EC020 overlaps instruction execution—that is, during bus activity for one instruction, instructions that do not use the external bus can be executed. Due to the independent operation of the on-chip cache relative to the operation of ...
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MC68020 Bus Arbitration The sequence of the MC68020 bus arbitration protocol is as follows external device asserts the BR signal. 2. The processor asserts the BG signal to indicate that the bus will become available at the ...
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PROCESSOR GRANT BUS ARBITRATION 1) ASSERT BG TERMINATE ARBITRATION 1) NEGATE BG AND WAIT FOR BGACK TO BE NEGATED RE-ARBITRATE OR RESUME PROCESSOR OPERATION Figure 5-42. MC68020 Bus Arbitration Flowchart for Single Request The timing diagram (see Figure 5-43) shows ...
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CLK A31–A0 FC2–FC0 SIZ1–SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31– BGACK PROCESSOR Figure 5-43. MC68020 Bus Arbitration Operation Timing for Single Request MOTOROLA DMA DEVICE M68020 USER’S MANUAL S0 S2 PROCESSOR 5- ...
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BUS REQUEST (MC68020). External devices capable of becoming bus masters request the bus by asserting BR. BR can be a wire-ORed signal (although it need not be constructed from open-collector devices) that indicates to the processor that some external ...
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BUS ARBITRATION CONTROL (MC68020). The bus arbitration control unit in the MC68020 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68020 are internally synchronized in a maximum of two cycles of the ...
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State changes occur on the next rising edge of the clock after the internal signal is recognized as valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The ...
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S4 CLK A31–A0 FC2–FC0 SIZ1–SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31– BGACK (ARBITRATION PERMITTED PROCESSOR WHILE THE PROCESSOR IS Figure 5-45. MC68020 Bus Arbitration Operation Timing—Bus Inactive MOTOROLA BUS INACTIVE ALTERNATE MASTER INACTIVE OR HALTED) ...
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MC68EC020 Bus Arbitration The sequence of the MC68EC020 bus arbitration protocol is as follows external device asserts the BR signal. 2. The processor asserts the BG signal to indicate that the bus will become available at the ...
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PROCESSOR GRANT BUS ARBITRATION 1) ASSERT BG RE-ARBITRATE OR RESUME PROCESSOR OPERATION Figure 5-46. MC68EC020 Bus Arbitration Flowchart for Single Request 5.7.2.1 BUS REQUEST (MC68EC020). External devices capable of becoming bus masters request the bus by asserting BR. BR can ...
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CLK A23–A0 FC2–FC0 SIZ1–SIZ0 R DSACK1 DSACK0 D31– PROCESSOR Figure 5-47. MC68EC020 Bus Arbitration Operation Timing for Single Request 5-72 DMA DEVICE M68020 USER’S MANUAL S0 S2 PROCESSOR MOTOROLA ...
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BUS ARBITRATION CONTROL (MC68EC020). The bus arbitration control unit in the MC68EC020 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68EC020 are internally synchronized in a maximum of two cycles of the ...
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State changes occur on the next rising edge of the clock after the internal signal is recognized as valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The ...
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S4 CLK A23–A0 FC2–FC0 SIZ1–SIZ0 R DSACK1 DSACK0 D31– (ARBITRATION PERMITTED PROCESSOR WHILE THE PROCESSOR IS Figure 5-49. MC68EC020 Bus Arbitration Operation Timing—Bus Inactive The existing three-wire arbitration design (BR, BG, and BGACK) of some peripherals ...
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An example of MC68EC020 bus arbitration to a DMA device that supports three-wire bus arbitration is described in Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol. Figure 5-50. Interface for Three-Wire to ...
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CLK + RESET BUS CYCLES BUS STATE UNKNOWN Figure 5-51. Initial Reset Operation Timing Resetting the processor causes any bus cycle in progress to terminate as if DSACK1/DSACK0 or BERR had been asserted. In addition, the processor ...
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CLK A31–A0 * FC2–FC0 SIZ1–SIZ0 R/W ** ECS ** OCS AS DS DSACK1 DSACK0 ** DBEN D31–D0 HALT RESET READ For the MC68EC020, A23–A0. * This signal does not apply to the MC68EC020. ** Figure 5-52. RESET ...
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SECTION 6 EXCEPTION PROCESSING Exception processing is defined as the activities performed by the processor in preparing to execute a handler routine for any condition that causes an exception. In particular, exception processing does not include execution of the handler ...
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For all exceptions other than reset, the third step is to save the current processor context. The processor creates an exception stack frame on the active supervisor stack and fills it with context information appropriate for the type of exception. ...
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Table 6-1. Exception Vector Assignments Vector Number 16– 32– ...
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Reset Exception Assertion of the RESET signal by external hardware causes a reset exception. For details on the requirements for the assertion of RESET , refer to Section 5 Bus Operation. The reset exception has the highest priority of ...
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Figure 6-1. Reset Operation Flowchart The processor begins exception processing for a bus error by making an internal copy of the current SR. The processor then enters the supervisor privilege level (by setting the S- bit in the SR) and ...
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The processor also saves the contents of some of its internal registers. The information saved on the stack is sufficient to identify the cause of the bus fault and recover from the error. For efficiency, the MC68020/EC020 ...
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The stack frame saves the trap vector offset, the PC, and the internal copy of the SR on the supervisor stack. The saved value of the PC is the logical address of ...
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Exception processing for illegal and unimplemented instructions is similar to that for instruction traps. When the processor has identified an illegal or unimplemented instruction, it initiates exception processing instead of attempting to execute the instruction. The processor copies the SR, ...
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Trace Exception To aid in program development, the M68000 processors include an instruction-by- instruction tracing capability. The MC68020/EC020 can be programmed to trace all instructions or only instructions that change program flow. In the trace mode, an instruction generates ...
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The exception processing for a trace starts at the end of normal processing for the traced instruction and ...
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Interrupt Exceptions When a peripheral device requires the services of the MC68020/EC020 or is ready to send information that the processor requires, it may signal the processor to take an interrupt exception. The interrupt exception transfers control to a ...
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OTHERWISE * IPEND is not implemented in the MC68EC020. Figure 6-2. Interrupt Pending Procedure Table 6-3. Interrupt Levels and Mask Values Requested Interrupt Level * Indicates that no interrupt is requested. ...
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MOTOROLA M68020 USER’S MANUAL 6- 13 ...
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However, if the MC68020/EC020 is handling a level 7 interrupt (I2–I0 in the SR set to 111) and the external request is lowered to level 3 and then raised back to level 7, a ...
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The MC68020 asserts IPEND (note that IPEND is not implemented in the MC68EC020) when it makes an interrupt request pending. Figure 6-4 shows the assertion of IPEND relative to the assertion of an interrupt level on IPL2 – IPL0 . ...
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EXIT THESE INDIVIDUAL BUS CYCLES MAY OCCUR IN ANY ORDER * Does not apply to the MC68EC020. Figure 6-5. Interrupt Exception Processing Flowchart 6-16 ONCE PER INSTRUCTION AT INSTRUCTION BOUNDARY OTHERWISE * IPEND ASSERTED * NEGATE IPEND EXECUTE INTERRUPT ACKNOWLEDGE ...
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For the MC68020 higher priority interrupt has been synchronized, the IPEND signal is negated during state 0 (S0 interrupt acknowledge cycle, and the IPL2–IPL0 signals for the interrupt being acknowledged can be negated at this time. ...
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Breakpoint Instruction Exception To use the MC68020/EC020 in a hardware emulator, it must provide a means of inserting breakpoints in the emulator code and of performing appropriate operations at each breakpoint. For the MC68000 and MC68008, this can be ...
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PIPE STAGE D INSTRUCTION WORD ON DATA BUS EXECUTE INSTRUCTION WORD EXIT Figure 6-6. Breakpoint Instruction Flowchart Table 6-4. Exception Priority Groups Group/ Priority Exception and Relative Priority 0 0.0—Reset 1 1.0—Address Error 1.1—Bus Error 2 2.0—BKPT, CALLM, CHK, CHK2, ...
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The priority scheme is very important in determining the order in which exception handlers execute when several exceptions occur at the same time general rule, the lower the priority of an exception, the sooner the handler routine for ...
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INVALID FORMAT WORD TAKE FORMAT ERROR EXCEPTION Figure 6-7. RTE Instruction for Throwaway Four-Word Frame For the coprocessor midinstruction stack frame, the processor reads the SR, PC, instruction address, internal register values, and the evaluated effective address from the stack, ...
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Refer to 6.2 Bus Fault Recovery for a description of the processing that occurs after the frame is read into the internal registers format error or bus error exception occurs ...
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Figure 6-8. Special Status Word Format FC—Fault on Stage C When the FC bit is set, the processor attempted to use stage C and found marked invalid due to ...
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B of the pipe are accepted as valid; the processor assumes that there is no prefetch pending for stage B and that software has repaired or filled the image of stage B, if necessary Rerun ...
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To repair data faults (indicated 1), the software should first examine the RM bit in the SSW to determine if the fault was generated during a read-modify-write operation the handler should then check ...
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FC) is cleared, the associated prefetch cycle may or may not be run by the RTE instruction (depending on whether the stage is required fault occurs when the RTE instruction attempts to rerun ...
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Table 6-5. Exception Stack Frames Stack Frames 15 SP STATUS REGISTER +$02 PROGRAM COUNTER +$ VECTOR OFFSET FOUR-WORD STACK FRAME — FORMAT $ STATUS REGISTER +$02 PROGRAM COUNTER +$ VECTOR ...
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Table 6-5. Exception Stack Frames (Continued) Stack Frames 15 SP STATUS REGISTER +$02 PROGRAM COUNTER +$ VECTOR OFFSET +$08 INTERNAL REGISTER +$0A SPECIAL STATUS REGISTER +$0C INSTRUCTION PIPE STAGE C +$0E INSTRUCTION PIPE STAGE B +$10 ...
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SECTION 7 COPROCESSOR INTERFACE DESCRIPTION The M68000 family of general-purpose microprocessors provides a level of performance that satisfies a wide range of computer applications. Special-purpose hardware, however, can often provide a higher level of performance for a specific application. The ...
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In contrast, standard peripheral hardware is generally accessed through interface registers mapped into the memory space of the main processor. To use the services provided by the peripheral, the programmer accesses the peripheral registers with standard processor instructions. While a ...
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Consequently, the programmer can assume that the images of registers and memory affected by a given instruction have been updated when the next instruction in the sequence accessing these registers ...
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MC68020/EC020 to begin exception processing. The MC68020/EC020 never generates coprocessor interface bus cycles with the CpID equal to zero (except via the MOVES instruction). CpID codes of 000–101 are reserved for current and future Motorola coprocessors, and CpID codes of ...
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To improve the efficiency of operand transfers between memory and the coprocessor, a coprocessor that requires a relatively high amount of bus bandwidth or has special bus requirements can be implemented as a DMA coprocessor. The DMA coprocessor provides all ...
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During coprocessor instruction execution, the MC68020/EC020 executes CPU space bus cycles to access the CIR set. The MC68020/EC020 asserts FC2–FC0, identifying a CPU space bus cycle. The CIR set is mapped into CPU space in the same manner that a ...
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CPU SPACE ADDRESS $20000 $2001F $22000 $2201F $24000 $2E000 $2E01F Figure 7-4. Coprocessor Address Map in MC68020/EC020 CPU Space 31 $00 RESPONSE $04 SAVE $08 OPERATION WORD $0C (RESERVED) $10 $14 REGISTER SELECT $18 $1C Figure 7-5. Coprocessor Interface Register ...
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M68000 coprocessor interface to indicate its status to the main processor. 7.2.1 Coprocessor General Instructions The coprocessor general instruction category contains data processing instructions and other ...
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MC68020/EC020 calculate an effective address during coprocessor instruction execution, information required for the calculation must be included in the instruction format as effective address extension words. 7.2.1.2 PROTOCOL. The execution of a cpGEN instruction follows ...
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MAIN PROCESSOR M1 RECOGNIZE COPROCESSOR INSTRUCTION F-LINE OPERATION WORD M2 WRITE COPROCESSOR COMMAND WORD TO COMMAND CIR M3 READ COPROCESSOR RESPONSE PRIMITIVE CODE FROM RESPONSE CIR 1) PERFORM SERVICE REQUESTED BY RESPONSE PRIMITIVE 2) IF (COPROCESSOR RESPONSE PRIMITIVE INDICATES "COME ...
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After evaluating the condition, the coprocessor returns a true/false indicator to the main processor by placing a null primitive (refer to 7.4.4 Null Primitive) in the response CIR. The main processor completes the coprocessor instruction execution when it receives the ...
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BRANCH ON COPROCESSOR CONDITION INSTRUCTION. The conditional instruction category includes two formats of the M68000 family branch instruction. These instructions branch on conditions related to the coprocessor operation. They execute similarly to the conditional branch instructions provided in the ...
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CIR to determine its next action. The coprocessor can MOTOROLA M68020 USER’S MANUAL 7- 13 ...
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If the coprocessor returns the false condition indicator, the main processor executes the next instruction in the instruction stream. If the coprocessor returns the true condition indicator, the ...
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The final portion of the cpScc instruction format contains zero to five effective address extension words. These words contain any additional information required to calculate the effective address specified by bits 5–0 of the F-line operation word. 7.2.2.2.2 Protocol. Figure ...
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If the coprocessor requires additional information to evaluate the condition, the cpDBcc instruction can include this information in extension words. These extension words follow the word containing the coprocessor condition selector field in the cpDBcc instruction format. The last word ...
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The second word of the cpTRAPcc instruction format contains the coprocessor condition selector in bits 5–0 and should contain zeros in bits 15–6 (these bits are reserved by Motorola) to maintain compatibility with future M68000 products. This word is written ...
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These coprocessor format codes are discussed in detail in 7.2.3.2 Coprocessor Format Words. 7.2.3.1 COPROCESSOR INTERNAL STATE FRAMES. The context save (cpSAVE) and context restore (cpRESTORE) instructions transfer an ...
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The information in a coprocessor state frame describes a context of operation for that coprocessor. This description of a coprocessor context includes the program invisible state information and, optionally, the program visible state information. The program invisible state information consists ...
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When the main processor reads the empty/reset format word from memory during the execution of the cpRESTORE instruction, it writes the format word to the restore CIR. The main processor then reads the restore CIR and, if the coprocessor returns ...
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CIR, it writes the abort mask to the control CIR and initiates format error exception processing (refer to 7.5.1.5 Format Errors). 7.2.3.2.4 Valid Format Word. When the main processor reads ...
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Protocol. Figure 7-16 shows the protocol for the coprocessor context save instruction. The main processor initiates execution of the cpSAVE instruction by reading the save CIR. Thus, the cpSAVE instruction is the only coprocessor instruction that begins by reading ...
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Following a cpSAVE instruction, the coprocessor should idle state—that is, not executing any coprocessor instructions. The cpSAVE instruction is a ...
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The instruction can include as many as five effective address extension words following the F-line operation word in the cpRESTORE instruction format. These words contain any additional information required to calculate the effective address specified by bits 5–0 of the ...
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After writing the format word to the restore CIR, the main processor continues cpRESTORE dialog by reading that same register. If the coprocessor returns a valid format word, the main processor transfers the number of bytes specified by the format ...
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When the MC68020/EC020 receives one of the three take exception coprocessor response primitives, it acknowledges the primitive by setting the exception acknowledge bit (XA) in the control CIR. The MC68020/EC020 sets the abort bit (AB) in the control CIR ...
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Condition CIR The main processor initiates a conditional category instruction by writing the condition selector to bits 5–0 of the 16-bit condition CIR. Bits 15–6 are undefined and reserved by Motorola. The offset from the base address of the ...
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Register Select CIR When the coprocessor requests the transfer of one or more main processor registers or a group of coprocessor registers, the main processor reads the 16-bit register select CIR to identify the number or type of registers ...
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ScanPC Several of the response primitives involve the scanPC, and many of them require the main processor to use it while performing services requested. These paragraphs describe the scanPC and its operation. During the execution of a coprocessor instruction, ...
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The encoding of bits 12– coprocessor response primitive depends on the individual primitive. Bits 15–13, however, specify optional additional operations that apply to most of the primitives defined for the M68000 coprocessor interface. The CA bit specifies the ...
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Busy Primitive The busy response primitive causes the main processor to reinitiate a coprocessor instruction. This primitive applies to instructions in the general and conditional categories. Figure 7-23 shows the format of the busy primitive ...
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Null Primitive The null coprocessor response primitive communicates coprocessor status information to the main processor. This primitive applies to instructions in the general and conditional categories. Figure 7-24 shows the format of the null primitive ...
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and then performs trace exception processing. When the main processor services pending interrupts before reading the response CIR again. A coprocessor can be designed to execute a cpGEN instruction concurrently with the execution ...
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Supervisor Check Primitive The supervisor check primitive verifies that the main processor is operating in the supervisor privilege level while executing a coprocessor instruction. This primitive applies to instructions in the general and conditional coprocessor instruction categories. Figure 7-25 ...
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The transfer operation word primitive uses the CA and PC bits as described in 7.4.2 Coprocessor Response Primitive General Format. If this primitive is issued with during a conditional category instruction, the main processor initiates protocol violation ...
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Evaluate and Transfer Effective Address Primitive The evaluate and transfer effective address primitive evaluates the effective address specified in the coprocessor instruction operation word and transfers the result to the coprocessor. This primitive applies to general category instructions. If ...
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The valid EA field of the primitive format specifies the valid effective address categories for this primitive. If the effective address specified in the instruction operation word is not a member of the class specified by the valid EA field, ...
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The DR bit specifies the direction of the operand transfer requests a transfer from the main processor to the coprocessor, and specifies a transfer from the coprocessor to the main processor. If the effective ...
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The write to previously evaluated effective address primitive uses the CA and PC bits as described in 7.4.2 Coprocessor Response Primitive General Format. The length field of the primitive format specifies the length of the operand in bytes. The MC68020/EC020 ...
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The take address and transfer data primitive described in 7.4.11 Take Address and Transfer Data Primitive does not replace the effective address value that has been calculated by the MC68020/EC020. The address that the main processor obtains in response to ...
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Transfer to/from Top of Stack Primitive The transfer to/from top of stack primitive transfers an operand between the coprocessor and the top of the active system stack of the main processor. This primitive applies to general and conditional category ...
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The D/A bit specifies whether the primitive transfers an address or data register. D indicates a data register, and D indicates an address register. The register field contains the register number the ...
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After reading a valid code from the register select CIR the main processor writes the long-word operand from the specified control register to the operand CIR the main processor reads a long-word ...
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Figure 7-37. Transfer Multiple Coprocessor Registers Primitive Format The transfer multiple coprocessor registers primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. The length ...
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For the predecrement addressing mode, the operands are written to memory with descending addresses, but the bytes within each operand are written to memory with ascending addresses example, Figure 7-38 shows the format in long-word- oriented memory for ...
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and the main processor writes the 16-bit SR value to the operand CIR and the main processor reads a 16-bit value from the operand CIR into ...
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Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the four-word stack frame format shown in Figure 7-41 +02 0 +06 ...