MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 32

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The value of the M-bit in the SR does not affect execution of privileged instructions; both
master and interrupt modes are at the supervisor privilege level. Instructions that affect the
M-bit are MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, and RTE. Also, the
processor automatically saves the M-bit value and clears it in the SR as part of exception
processing for interrupts.
All exception processing is performed at the supervisor privilege level. All bus cycles
generated during exception processing are supervisor references, and all stack accesses
use the active SSP.
2.1.2 User Privilege Level
The user level is the lower privilege level. The privilege level is determined by the S-bit of
the SR; if the S-bit is clear, the processor executes instructions at the user privilege level.
Most instructions execute at either privilege level, but some instructions that have
important system effects are privileged and can only be executed at the supervisor level.
For instance, user programs are not allowed to execute the STOP instruction or the
RESET instruction. To prevent a user program from entering the supervisor privilege level
except in a controlled manner, instructions that can alter the S-bit in the SR are privileged.
The TRAP #n instruction provides controlled access to operating system services for user
programs.
The bus cycles for an instruction executed at the user privilege level are classified as user
references, and the values of the FC2–FC0 signals specify user address spaces. While
the processor is at the user level, references to the system stack pointer implicitly, or to
address register seven (A7) explicitly, refer to the USP.
2.1.3 Changing Privilege Level
To change from the user to the supervisor privilege level, one of the conditions that
causes the processor to perform exception processing must occur. This causes a change
from the user level to the supervisor level and can cause a change from the master mode
to the interrupt mode. Exception processing saves the current values of the S and M bits
of the SR (along with the rest of the SR) on the active supervisor stack, and then sets the
S-bit, forcing the processor into the supervisor privilege level. When the exception being
processed is an interrupt and the M-bit is set, the M-bit is cleared, putting the processor
into the interrupt mode. Execution of instructions continues at the supervisor level to
process the exception condition.
To return to the user privilege level, a system routine must execute one of the following
instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These
instructions execute at the supervisor privilege level and can modify the S-bit of the SR.
After these instructions execute, the instruction pipeline is flushed and is refilled from the
appropriate address space.
The RTE instruction returns to the program that was executing when the exception
occurred. It restores the exception stack frame saved on the supervisor stack. If the frame
MOTOROLA
M68020 USER’S MANUAL
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