MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 54

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The multiplexer takes the four bytes of the 32-bit bus and routes them to their required
positions. For example, OP0 can be routed to D31–D24, as would be the normal case, or
it can be routed to any other byte position to support a misaligned transfer. The same is
true for any of the operand bytes. The positioning of bytes is determined by the SIZ1,
SIZ0, A1, and A0 outputs.
The SIZ1 and SIZ0 outputs indicate the remaining number of bytes to be transferred
during the current bus cycle, as listed in Table 5-2.
The number of bytes transferred during a write or read bus cycle is equal to or less than
the size indicated by the SIZ1 and SIZ0 outputs, depending on port width and operand
alignment. For example, during the first bus cycle of a long-word transfer to a word port,
the SIZ1 and SIZ0 outputs indicate that four bytes are to be transferred, although only two
bytes are moved on that bus cycle.
A1–A0 also affect operation of the data multiplexer. During an operand transfer, A31–A2
(for the MC68020) or A23–A2 (for the MC68EC020) indicate the long-word base address
of that portion of the operand to be accessed; A1 and A0 indicate the byte offset from the
base. Table 5-3 lists the encodings of A1 and A0 and the corresponding byte offsets from
the long-word base.
MOTOROLA
Table 5-2. SIZ1, SIZ0 Signal Encoding
Asserted
Asserted
Asserted
Asserted
Negated
Negated
Negated
Negated
Table 5-3. Address Offset Encodings
SIZ1
A1
M68020 USER’S MANUAL
Asserted
Asserted
Asserted
Asserted
Negated
Negated
Negated
Negated
SIZ0
A0
Long Word
+0 Bytes
+2 Bytes
+3 Bytes
+1 Byte
3 Bytes
Offset
Word
Size
Byte
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