MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 365

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9
9-64
tialize the ATC to minimize table searching during program execution. Any
all history information in the translation tables (used and modified bits) as
The PTEST instruction either searches the ATC or performs a table search
operation for a specified function code and logical address, and sets the
the search. The physical address of the last descriptor fetched can be returned
alter the ATC.
This instruction is primarily used in bus error handling routines. For example,
This instruction requests that the MC68030 search the translation tables for
offset]). The MC68030 is instructed to search to the bottom of the table (#7
- -
the last table entry used in register A0. After executing this instruction, the
the logical address and the R/W bit of that register is not masked.
tions with CplD=0 (including MC68851 instructions) that the MC68030 does
The PFLUSH instruction flushes (invalidates) address translation descriptors
The PFLUSH instruction flushes all entries with a specified function code or
the entry with a specified function code and logical address.
The PLOAD instruction performs a table search operation for a specified
function code and logical address and then loads the translation for the
address into the ATC. The operating system can use this instruction to ini-
existing entry in the ATC that translates the specified address is flushed. The
preload can be executed for either read or write attributes. If the write attribute
is selected (PLOADW), the MC68030 performs the table search and updates
if a write operation to that address had occurred. Similarly, if the read attribute
is selected (PLOADR), the history information in the translation table (used
bit) is updated as if a read operation had occurred. The PLOAD instruction
does not alter the MMUSR.
appropriate bits in the MMUSR to indicate conditions encountered during
in an address register. The exception routines of the operating system can
use this instruction to identify MMU faults. The PTEST instruction does not
if a bus error has occurred, the handler can execute an instruction such as:
an address in user data space (#1) and examine protection information. This
particular logical address is obtained from the exception stack frame ([A7,
handler can examine the MMUSR for the source of the fault and use A0 to
access the last descriptor. Note that the PTESTR and PTESTW instructions
The MMU instructions use the same opcodes and coprocessor identification
(CplD) as the corresponding instructions of the MC68851. All F-line instruc-
in the ATC. PFLUSHA, a version of the PFLUSH instruction, flushes all entries.
have identical results except for PTEST0 when either TTx register matches
there cannot be more than six levels) and return the physical address of
PTESTW
M C 6 8 0 3 0 U S E R ' S M A N U A L
#1,([A7, offset]),#7,A0
M O T O R O L A