MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 586

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

C;BREQ Signal, 5-7, 6-16-6-20, 7-6, 7-30, 7-48ff,
Clear Data Cache Bit, 6-21
Clear Entry in Data Cache Bit, 6-21
Clock Signal, 5-11, 7-54ff
Command CIR, 10-31
Command Words, Illegal, Coprocessor Detected,
Cache Inhibit Input Signal, 5-7, 6-3, 6-9-6-11, 6-15,
Cache Inhibit Output Signal, 5-7, 6-3, 6-9, 7-30ff,
CACR, 1-9, 2-5, 6-3, 6-4, 6-20-6-22
Calculate Effective Address Timing Table, 11-31
Calculate Immediate Effective Address Timing
Calculations, Execution Time, 11-5ff
Capabilities, Addressing, 2-25
CAS Instruction, 7-43
Case,
CAS2 Instruction, 7-43
CBACK Signal, 5-7, 6-16, 7-6, 7-30ff
CCR, 2-4, 3-14
CD Bit, 6-21
CDIS Signal, 5-10, 6-3
CED Bit, 6-21
CEI Bit, 6-22
Changing Privilege Level, 4-4
C~ Bit, 6-22
CIIN Signal, 5-7, 6-3, 6-9-6-11, 6-15, 7-3, 7-26ff,
CLOUT Signal, 5-7, 6-3, 6-9, 7-30ff, 9-2, 9-17
CIR, 10-8, 10-29
Clear Entry in Instruction Cache Bit, 6-22
Clear Instruction Cache Bit, 6-22
CLK Signal, 5-11, 7-54ff
Compare and Swap Instruction, 7-43
Compatibility, M68000 Addressing, 2-36
Computation, Condition Code, 3-15
Concurrent Operation, 10-3
Condition CIR, 10-31
Condition Code
MOTOROLA
7-3, 7-26ff
Table, 11-33
Actual Instruction Cache, 11-11
Average No Cache, 11-8
Command, 10-31
Condition, 10-31
Control, 10-30
Operand, 10-32
Operand Address, 10-33
Operation Word, 10-31
Register Select, 10-32
Response, 10-29
Restore, 10-31
Save, 10-30
Computation, 3-15
9-1, 9-13
Example, 3-25
Best, 11-7
Instruction Cache, 11-6
Example, 3-25
Instruction Address, 10-33
10-63
Register, 2-4, 3-14
MC68030 USER'S MANUAL
Condition Tests, 3-17
Conditional Branch Instruction Timing Table, 11-48
Connections, Power Supply, 5-11
Considerations,
Contiguous Memory, 9-33, 9-35
Control,
Control CIR, 10-30
Control Instruction Timing Table, 11-49
Controller,
Coprocessor,
Coprocessor Detected
Coprocessor Interface Register, 10-8, 10-29
Count, Initial Shift, 9-69
CplD, 7-74, 10-4
cpBcc Instruction, 10-14
cpDBcc Instruction, 10-17
cpRESTORE Instruction, 10-27
cpSAVE instruction, 10-25
cpScc Instruction, 10-15
cpTRAPcc Instruction, 10-18
cpTRAPcc Instruction Exception, 10-69
CPU Root Pointer, 1-9, 2-5, 9-23, 9-52, 9-54, 9-65
CPU Space, 7-68, 7-70, 10-5ff
CPU Space Address Encoding, 7-68
CRP, 1-9, 2-5, 9-23, 9-52, 9-54, 9-65
Ground, 12-43
Example,
Early Termination, 12-34
Power, 12-43
Bus Arbitration, 7-100
Bus, 11-5
Micro Bus, 11-5
Communication Cycle,
Conditional Instructions, 10-12
Context Restore Instruction, 10-27
Context Save Instruction, 10-24
Data Processing Exceptions, 10-66
DMA, 10-6
Format Words, 10-22
General Instruction Protocol, 10-11
General Instructions, 10-9
Identification Code, 10-4
Instruction Format, 10-4
Instruction Summary, 10-72-10-75
Instructions, 3-21
Interface, 10-1, 10-6
MC68881, 12-4
MC68882, 12-4
Reset, 10-72
State Frames, 10-21
System Related Exceptions, 10-64
Exceptions, 10-61
Non-DMA, 10-6
Response Primitive, 10-33
Response Primitive Format, 10-35
Format Errors, 10-64
Illegal Command Words, 10-63
Illegal Condition Words, 10-63
Protocol Violations, 10-62
9-35
7-74
INDEX-3