MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 585

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Bit Field
Bit Manipulation
Block Diagram, 1-2, 9-3
BR Signal, 5-8, 7-43, 7-60, 7-96ff
Branch on Coprocessor Condition Instruction, 10-13
BKPT Instruction, 7-74, 8-15, 8-22
Breakpoint Acknowledge, 8-10
Breakpoint Instruction, 7-74, 8-22
Buffer,
Burst
Bus,
Bit (Continued)
INDEX-2
Enable Data Cache, 6-22
Enable Instruction Cache, 6-23
WA, 6-21
Write Allocate, 6-21
Operations, 3-31
Write Pending, 11-5
Clear Entry in Data Cache, 6-21
Clear Entry in Instruction Cache, 6-22
Clear Instruction Cache, 6-22
Data Burst Enable, 6-21
DBE, 6-21
DR, 10-36
ED, 6-22
El, 6-23
FD, 6-22
FI, 6-23
Freeze Data Cache, 6-22
Freeze Instruction Cache, 6-23
IBE, 6-22
Instruction Burst Enable, 6-22
PC, 10-35
Instruction Timing Table, 11-47
Instructions, 3-9
Instruction Timing TaMe, 11-46
Instructions, 3-9
MMU, 9-3
Processor Resource, 11-4
Cycle, 7-74
Flowchart, 7-75
Exception, 8-22
Instruction Fetch Pending, 11-5
Cycle, 7-59, 12-17
Mode
Operation, 7-59
Address, 5-4, 7-3, 7-30ff, 12-5
Arbitration, 7-96
Exception Signaled, Timing, 7-77
Timing, 7-76
State Diagram, 7-101
Timing, 7-99
Cache Filling, 6-10
Static RAM, 12-18-12-24
Flowchart, 7-62
Bus Inactive, Timing, 7-104
Control, 7-100
Flowchart, 7-98
Latency, 11-62
MC68030 USER'S MANUAL
Bus Grant, 7-99
Bus Grant Acknowledge, 7-100
Bus Request, 7-98
Busy Primitive, 10-36
Byte
CA Bit, 10-35
CAAR, 1-9, 2-5, 6-23
Cache,
Cache Address Register, 1-9, 2-5, 6-23
Cache Disable Signal, 5-10, 6-3
Cache Burst Acknowledge Signal, 5-7, 6-16-6-20,
Cache Burst Request Signal, 5-7, 6-16-6-20, 7-6,
Cache Control Register, 1-9, 2-5, 6-1, 6-3, 6-20, 6-21
Control Signals, 7-3
Controller, 11-5
Data, 5-4, 7-5, 7-30ff, 12-9, 12-19
Error,
Errors, 7-82
Exceptions, 7-75
Fault Recovery, 8-27
Operation,
Synchronization, 7-95
Transfer Signals, 7-1
Signal, 5-9, 7-43, 7-96ff
Signal, 5-9, 7-97ff
Signal, 5-8, 7-43, 7-60, 7-96ff
Write Cycle, Asynchronous, 32-Bit Port, Timing,
Data Select, 7-25
Read Cycle, Asynchronous,
Select Logic, 12-9-12-12
Address Translation, 7-3, 9-4, 9-17
7-30, 7-48ff
Data, 1-16, 6-6, 11-4, 11-16
External, 12-30-12-32
Filling, 7-24
Instruction, 1-16, 6-1, 6-4, 11-4
Interactions, 7-26
Organization, 6-1
Reset, 6-20
7-6, 7-30ff
Without DSACKx Timing, 7-84
Asynchronous, 7-27
Timing, 7-96
Late, STERM, Timing, 7-86
Second Access, Timing, 7-88
Exception, 8-7, 10-71
Signal, 5-9, 6-11, 7-6, 7-27ff, 8-7, 8-22
Synchronous, 7-28, 7-29
32-Bit Port, Timing, 7-33
Late, Third Access, Timing, 7-87
Late, With DSACKx, Timing, 7-85
Flowchart, 7-32
7-38
Burst Mode, 6-15
Single Entry, 6-10
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