MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 126

• Manufacturer Part Number: MC68020CRC16E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
SECTION 6
EXCEPTION PROCESSING
Exception processing is defined as the activities performed by the processor in preparing
to execute a handler routine for any condition that causes an exception. In particular,
exception processing does not include execution of the handler routine itself. An
introduction to exception processing, as one of the processing states of the
MC68020/EC020, is given in Section 2 Processing States.
This section describes exception processing in detail, describing the processing for each
type of exception. It describes the return from an exception and bus fault recovery. This
section also describes the formats of the exception stack frames. For more detail on
protocol violation and coprocessor-related exceptions, refer to Section 7 Coprocessor
Interface Description. Also, for more detail on exceptions defined for floating-point
coprocessors, refer to MC68881UM/AD , MC68881/MC68882 Floating-Point Coprocessor
User's Manual .
6.1 EXCEPTION PROCESSING SEQUENCE
Exception processing occurs in four functional steps. However, all individual bus cycles
associated with exception processing (vector acquisition, stacking, etc.) are not
guaranteed to occur in the order in which they are described in this section. Nonetheless,
all addresses and offsets from the stack pointer are guaranteed to be as described.
The first step of exception processing involves the SR. The processor makes an internal
copy of the SR, then sets the S-bit in the SR, changing to the supervisor privilege level.
Next, the processor inhibits tracing of the exception handler by clearing the T1 and T0 bits
in the SR. For the reset and interrupt exceptions, the processor also updates the interrupt
priority mask (bits 10–8 of the SR).
In the second step, the processor determines the vector number of the exception. For
interrupts, the processor performs an interrupt acknowledge cycle (a read from the CPU
address space type 1111; see Figures 5-32 and 5-33) to obtain the vector number. For
coprocessor-detected exceptions, the vector number is included in the coprocessor
exception primitive response. (Refer to Section 7 Coprocessor Interface Description for
a complete discussion of coprocessor exceptions.) For all other exceptions, internal logic
provides the vector number. This vector number is used in the last step to calculate the
address of the exception vector. Throughout this section, vector numbers are given in
decimal notation.
MOTOROLA
M68020 USER’S MANUAL
6- 1
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