MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 303

• Manufacturer Part Number: MC68020CRC16E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

FC2–FC0 Signals, 2-2, 2-4, 3-2, 5-2, 5-3,
Features, 1-2
F-Line Operation Words, 7-3
Floating-Point Coprocessor, 7-1, 9-1
Flowchart
Format Error Exception, 6-10
Ground Connections, 3-7, 9-9
HALT Signal, 3-7, 5-4, 5-25, 5-53, 5-60
Idle Clock Cycles, 8-7
Illegal Instruction Exception, 6-7
Instruction
MOTOROLA
5-44, 7-6
Breakpoint Acknowledge Cycle, 5-50
Byte Read Cycle, 5-26
Interrupt Acknowledge Cycle, 5-46
Long-Word Read Cycle, 5-26
MC68EC020 Bus A rbitration, 5-70
MC68020 Bus A rbitration, 5-63
Read-Modify-Write Cycle, 5-39
Reset Exception, 6-4
Write Cycle, 5-33
Arithmetic/Logical, 8-30, 8-31
Bcc, 8-37
Bit Field Manipulation, 8-36
Bit Manipulation, 8-35
BKPT, 5-50
CALLM, 9-14, 9-16, 9-18
CAS, 5-39
CAS2, 5-39
Control, 8-38
Coprocessor Conditional Instructions, 7-10
Coprocessor Context Restore Instruction
Coprocessor Context Save Instruction
Coprocessor Instruction, 6-25, 7-1, 7-3, 7-7
Coprocessor Instruction Execution, 7-6
Category, 7-22
Category, 7-20
— G —
— H —
— F —
— I —
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USER’S MANUAL
Go to: www.freescale.com
Instruction Execution, 5-62, 8-1
Instruction Execution Overlap, 8-4
Instruction Pipe, 1-12, 4-1, 6-21
Instruction Prefetches, 8-1
Instruction Set, 1-10
Instruction Timing, 8-8, 8-9
Internal Cache Holding Register, 5-21
Interrupt, 6-1
Interrupt Acknowledge Cycle, 5-4, 5-45, 6-16
Interrupt Exception, 5-45, 6-11
Interrupt Priority Mask, 5-45, 6-11
Interrupt Stack Pointer (ISP), 1-4, 2-2
IPEND Signal, 3-5, 6-14
IPL2–IPL0 Signals 3-5, 5-45, 6-11
Coprocessor Context Save and Context
Coprocessor General Instruction Category,
cpBcc, 7-12
cpDBcc, 7-14
cpRESTORE, 7-17, 7-22
cpSAVE, 7-17, 7-20
cpScc, 7-13
cpTRAPcc, 7-15, 7-55
Exception-Related, 8-39
Illegal Instruction, 6-7
MOVE, 8-20
MOVE SR, 8-3
MOVEA, 8-20
MOVEC, 4-3
NOP, 5-62, 8-3
Prefetches, 4-1
Primitive Instructions, 7-27
RESET, 5-76, 7-58
RTE, 6-19, 6-24
RTM, 9-14, 9-16, 9-19
Shift/Rotate, 8-34
Single-Operand Instructions, 8-33
Special-Purpose MOVE, 8-29
STOP, 6-10
TAS, 5-39
Unimplemented Instruction, 6-7
Flowchart, 6-14
Interrupt Exception, 6-11
Nonmaskable, 6-12
Timing, 5-46
Restore Instruction Categories, 7-16
7-8
INDEX-3