MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 143

• Manufacturer Part Number: MC68020CRC16E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
6.1.10 Breakpoint Instruction Exception
To use the MC68020/EC020 in a hardware emulator, it must provide a means of inserting
breakpoints in the emulator code and of performing appropriate operations at each
breakpoint. For the MC68000 and MC68008, this can be done by inserting an illegal
instruction at the breakpoint and detecting the illegal instruction exception from its vector
location. However, since the VBR on M68000 family processors MC68010 and later
allows arbitrary relocation of exception vectors, the exception address cannot reliably
identify a breakpoint. The MC68020/EC020 processor provides a breakpoint capability
with a set of breakpoint instructions, $4848–$484F, for eight unique breakpoints. The
breakpoint facility also allows external hardware to monitor the execution of a program
residing in the on-chip instruction cache without severe performance degradation.
When the MC68020/EC020 executes a breakpoint instruction, it performs a breakpoint
acknowledge cycle (read cycle) from CPU space type $0 with address lines A4–A2
corresponding to the breakpoint number. Refer to Section 5 Bus Operation for a
description of the breakpoint acknowledge cycle. The external hardware can return either
BERR or DSACK1/DSACK0 with an instruction word on the data bus. If the bus cycle
terminates with BERR , the processor performs illegal instruction exception processing. If
the bus cycle terminates with DSACK1/DSACK0 , the processor uses the data returned to
replace the breakpoint instruction in the internal instruction pipe and begins execution of
that instruction. The remainder of the pipe remains unaltered. In addition, no stacking or
vector fetching is involved with the execution of the instruction. Figure 6-6 is a flowchart of
the breakpoint instruction execution.
6.1.11 Multiple Exceptions
When several exceptions occur simultaneously, they are processed according to a fixed
priority. Table 6-4 lists the exceptions grouped by characteristics. Each group has a
priority from 4–0. Priority 0 has the highest priority.
As soon as the MC68020/EC020 has completed exception processing for a condition
when another exception is pending, it begins exception processing for the pending
exception instead of executing the exception handler for the original exception condition.
Also, whenever a bus error or address error occurs, its exception processing takes
precedence over lower priority exceptions and occurs immediately. For example, if a bus
error occurs during the exception processing for a trace condition, the system processes
the bus error and executes its handler before completing the trace exception processing.
However, most exceptions cannot occur during exception processing, and very few
combinations of the exceptions shown in Table 6-4 can be pending simultaneously.
6-18
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