MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 93

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MC68020CRC16E

Manufacturer Part Number
MC68020CRC16E
Description
IC MICROPROCESSOR 32BIT 114-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68020CRC16E

Processor Type
M680x0 32-Bit
Speed
166MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
114-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16.67MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
114
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68020CRC16E
Manufacturer:
MOT
Quantity:
10
The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in
5.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences
are:
The responding device places the vector number on the data bus during the interrupt
acknowledge cycle. Beyond this, the cycle is terminated normally with DSACK1/DSACK0.
Figure 5-32 is the flowchart of the interrupt acknowledge cycle.
Figure 5-33 shows the timing for an interrupt acknowledge cycle terminated with
DSACK1/DSACK0.
5-46
1. FC2–FC0 are set 111 for CPU address space.
2. A3, A2, and A1 are set to the interrupt request level (the inverted values of IPL2,
3. The CPU space type field (A19–A16) is set to 1111, the interrupt acknowledge code.
4. Other address signals (A31–A20, A15–A4, and A0 for the MC68020; A23–A20,
*
*
This step does not apply to the MC68EC020.
1) INTERRUPT PENDING CONDITION (IPEND FOR
MC68020) RECOGNIZED BY CURRENT INSTRUC-
TION—WAIT FOR INSTRUCTION BOUNDARY.
2) SET R/W TO READ
3) SET FUNCTION CODE TO CPU SPACE
4) PLACE INTERRUPT LEVEL ON A1, A2, AND A3.
5) SET SIZE TO BYTE
6) NEGATE IPEND
7) ASSERT AS AND DS
1) LATCH VECTOR NUMBER
2) NEGATE AS AND DS
IPL1, and IPL0, respectively).
A15–A4, and A0 for the MC68EC020) are set to one.
CONTINUE INTERRUPT EXCEPTION PROCESSING
TYPE FIELD = IACK
ACKNOWLEDGE INTERRUPT
ACQUIRE VECTOR NUMBER
PROCESSOR
Figure 5-32. Interrupt Acknowledge Cycle Flowchart
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USER’S MANUAL
Go to: www.freescale.com
1) PLACE VECTOR NUMBER ON LEAST
2) ASSERT DSACK1/DSACK0
1) REMOVE VECTOR NUMBER FROM DATA BUS
2) NEGATE DSACK1/DSACK0
SIGNIFICANT BYTE OF DATA PORT
(DEPENDS ON PORT SIZE)
ASSERT AVEC FOR AUTOMATIC GENERA-
TION OF VECTOR NUMBER
PROVIDE VECTOR INFORMATION
INTERRUPTING DEVICE
REQUEST INTERRUPT
RELEASE
OR
MOTOROLA

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