MPC8572EPXAVND Freescale Semiconductor, MPC8572EPXAVND Datasheet - Page 125

• Manufacturer Part Number: MPC8572EPXAVND
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572EPXAVND

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.5GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

AV
frequency. All traces should be kept short, wide and direct.
21.3
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8572E system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V
of the device. These decoupling capacitors should receive their power from separate V
OV
inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others
may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
Additionally, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
21.4
The SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SV
XV
appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
Freescale Semiconductor
DD
DD
DD
_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
, GV
_SRDSn) to ensure low jitter on transmit and reliable recovery of data in the receiver. An
Decoupling Recommendations
SerDes Block Power Supply Decoupling Recommendations
DD
DD
, and LV
AV
Signals on the SerDesn interface are fed from the XV
plane.
SV
, TV
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
DD_SRDSn
DD
DD
_SRDSn should be a filtered version of SV
DD
, BV
1. An 0805 sized capacitor is recommended for system initial bring-up.
, and GND power planes in the PCB, utilizing short traces to minimize
DD
Figure 63. SerDes PLL Power Supply Filter
, OV
1.0 Ω
DD
, GV
2.2 µF
DD
, and LV
NOTE
NOTE
1
GND
DD
DD
2.2 µF
planes, to enable quick recharging of the
, TV
1
DD
DD
, BV
_SRDSn.
DD
0.003 µF
_SRDSn power
DD
, OV
AV
DD
DD
, GV
System Design Information
_SRDSn
DD,
DD
DD
, and LV
TV
_SRDSn and
DD
, BV
DD
DD
pin
125
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