MPC8572EPXAVND Freescale Semiconductor, MPC8572EPXAVND Datasheet - Page 47

• Manufacturer Part Number: MPC8572EPXAVND
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572EPXAVND

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.5GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8.3.4
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver
characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver
inputs (SD2_RX[n] and SD2_RX[n]) as depicted in
8.3.4.1
Table 40
8.3.4.2
Table 41
supported. Clock is recovered from the data.
eye diagram.
Freescale Semiconductor
At recommended operating conditions with XV
At recommended operating conditions with XV
Deterministic Jitter Tolerance
Combined Deterministic and Random Jitter Tolerance
Sinusoidal Jitter Tolerance
Total Jitter Tolerance
Bit Error Ratio
Unit Interval
AC Coupling Capacitor
Notes:
1. Measured at receiver.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.
4. See RapidIO 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications.
Deterministic Jitter
Total Jitter
Unit Interval
V
V
Notes:
1. Each UI is 800 ps ± 100 ppm.
OD
OD
provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.
provides the SGMII receive AC timing specifications. Source synchronous clocking is not
fall time (80%-20%)
rise time (20%-80%)
SGMII AC Timing Specifications
SGMII Transmit AC Timing Specifications
SGMII Receive AC Timing Specifications
Parameter
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter
Table 40. SGMII Transmit AC Timing Specifications
Table 41. SGMII Receive AC Timing Specifications
DD_SRDS2
DD_SRDS2
Symbol
t
tfall
JD
JT
UI
rise
= 1.1V ± 5%.
= 1.1V ± 5%.
Figure 24
799.92
Symbol
Min
JSIN
BER
JDR
—
—
50
50
C
JD
JT
UI
TX
Figure
shows the SGMII receiver input compliance mask
799.92
Typ
800
25, respectively.
0.37
0.55
0.65
Min
—
—
—
—
0.1
—
5
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
800.08
Typ
800
—
—
—
—
—
—
Max
0.17
0.35
120
120
800.08
10
Max
200
—
—
—
—
-12
UI p-p
UI p-p
Unit
ps
ps
ps
UI p-p
UI p-p
UI p-p
UI p-p
Unit
nF
ps
—
Notes
—
—
—
—
1
Notes
—
1
1
1
1
2
3
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