TN80C188EA20 Intel, TN80C188EA20 Datasheet - Page 14

• Manufacturer Part Number: TN80C188EA20
• Description: IC MPU 16-BIT 5V 20MHZ 68-PLCC
• Manufacturer: Intel

Specifications of TN80C188EA20

• Rohs Status: RoHS non-compliant
• Processor Type: 80C188
• Features: EA suffix, 16-Bit, Extended Temp
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Other names: 803497

80C186EA 80C188EA 80L186EA 80L188EA
NOTE
Pin names in parentheses apply to the 80C188EA and 80L188EA
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MCS0 PEREQ
MCS1 ERROR
MCS2
MCS3 NCS
PCS4 0
PCS5 A1
PCS6 A2
T0OUT
T1OUT
T0IN
T1IN
DRQ0
DRQ1
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
N C
Name
Pin
Type
Pin
I O
I O
O
O
O
I
I
I
A(E L)
A(E L)
Input
Type
A(L)
A(L)
A(E)
A(L)
Table 3 Pin Descriptions (Continued)
H(1) H(X)
Output
States
H(Q)
H(1)
R(1)
H(1)
R(1)
R(1)
R(1)
P(Q)
H(1)
R(Z)
P(1)
P(1)
P(1)
P(1)
These pins provide a multiplexed function If enabled
these pins normally comprise a block of Mid-Range Chip
Select outputs which will go active whenever the address
of a memory bus cycle is within the address limitations
programmed by the user In Numerics Mode (80C186EA
only) three of the pins become handshaking pins for the
80C187 The CoProcessor REQuest input signals that a
data transfer is pending ERROR is an input which
indicates that the previous numerics coprocessor
operation resulted in an exception condition An interrupt
Type 16 is generated when ERROR is sampled active at
the beginning of a numerics operation Numerics
Coprocessor Select is an output signal generated when
the processor accesses the 80C187
Peripheral Chip Selects go active whenever the address
of a memory or I O bus cycle is within the address
limitations programmed by the user
These pins provide a multiplexed function As additional
Peripheral Chip Selects they go active whenever the
address of a memory or I O bus cycle is within the
address limitations by the user They may also be
programmed to provide latched Address A2 1 signals
Timer OUTput pins can be programmed to provide a
single clock or continuous waveform generation
depending on the timer mode selected
Timer INput is used either as clock or control signals
depending on the timer mode selected
DMA ReQuest is asserted by an external request when it
is prepared for a DMA transfer
Maskable INTerrupt input will cause a vector to a specific
Type interrupt routine To allow interrupt expansion INT0
and or INT1 can be used with INTA0 and INTA1 to
interface with an external slave controller INT1 becomes
SELECT when the ICU is configured for Slave Mode
These pins provide multiplexed functions As inputs they
provide a maskable INTerrupt that will cause the CPU to
vector to a specific Type interrupt routine As outputs
each is programmatically controlled to provide an
INTerrupt Acknowledge handshake signal to allow
interrupt expansion INT3 INTA1 becomes IRQ when the
ICU is configured for Slave Mode
No Connect For compatibility with future products do not
connect to these pins
Description
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