FWIXP420BB Intel, FWIXP420BB Datasheet - Page 19
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FWIXP420BB
Manufacturer Part Number
FWIXP420BB
Description
IC NETWRK PROCESSR 266MHZ 492BGA
Manufacturer
Intel
Specifications of FWIXP420BB
Processor Type
Network
Features
XScale Core
Speed
266MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
492-BGA
Core Operating Frequency
266MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
852278
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FWIXP420BB
Manufacturer:
MICRON
Quantity:
2 198
Part Number:
FWIXP420BB
Manufacturer:
INTEL
Quantity:
20 000
Datasheet
2.1.2.2
2.1.2.3
2.1.3
Once the AHB/AHB bridge has obtained the read information from the peripheral on the South
AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/AHB bridge has
the data for the master that requested the “split” transfer. The master on the North AHB — that
requested the split transfer — will arbitrate for the North AHB and transfer the read data from the
AHB/AHB bridge. The North AHB is released to complete another transaction while the North
AHB master — that requested the “split” transfer — waits for the data to arrive.
These “posting” and “splitting” transfers allow control of the North AHB to be given to another
master on the North AHB — enabling the North AHB to achieve maximum efficiency. Transfers to
the AHB/AHB bridge are considered to be small and infrequent, relative to the traffic passed
between the NPEs on the North AHB and the SDRAM.
South AHB
The South AHB is a 133.32-MHz, 32-bit bus that can be mastered by the Intel XScale
controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the SDRAM, PCI
interface, queue manager, expansion bus, or the APB/AHB bridge.
Accessing across the APB/AHB bridge allows interfacing to peripherals attached to the APB.
APB Bus
The APB Bus is a 66.66-MHz (which is 2 * OSC_IN input pin.), 32-bit bus that can be mastered by
the AHB/APB bridge only. The targets of the APB bus can be:
The APB interface is also used as an alternate-path interface to the NPEs and is used for NPE code
download and configuration.
MII Interfaces
Two industry-standard, media-independent interface (MII) interfaces are integrated into most of
the IXP42X product line and IXC1100 control plane processors with separate media-access
controllers and independent network processing engines. (See
The independent NPEs and MACs allow parallel processing of data traffic on the MII interfaces
and off-loading of processing required by the Intel XScale
IXC1100 control plane processors are compliant with the IEEE, 802.3 specification.
In addition to two MII interfaces, the IXP42X product line and IXC1100 control plane processors
include a single management data interface that is used to configure and control PHY devices that
are connected to the MII interface.
•
•
•
•
High-speed UART interface
USB v 1.1 interface
Internal bus performance monitoring unit
(IBPMU)
GPIO
Intel
®
IXP42X Product Line and IXC1100 Control Plane Processor
•
•
•
•
Console UART interface
All NPEs
Interrupt controller
Timers
®
Core. The IXP42X product line and
Table 3 on page
Functional Overview
17.)
®
Core, PCI
19