QU80386EXTC25 Intel, QU80386EXTC25 Datasheet - Page 22

• Manufacturer Part Number: QU80386EXTC25
• Description: IC INT PROC 5V 25MHZ 132QFP
• Manufacturer: Intel

Specifications of QU80386EXTC25

• Processor Type: 386EX
• Features: 32-bit, Extended Temp
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863826

Intel386™ EX Embedded Microprocessor
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or terminating a DMA process. The Target is the device with which the Requestor wishes to
communicate. The DMA process considers the Target a slave that is incapable of controlling the
process. The Byte Count dictates the amount of data that must be transferred.
Refresh Control Unit
The Refresh Control Unit (RCU) simplifies dynamic memory controller design with its integrated
address and clock counters. Integrating the RCU into the processor allows an external DRAM
controller to use chip-selects, wait state logic, and status lines.
The Refresh Control Unit:
The RCU contains a 13-bit address counter that forms the refresh address, supporting DRAMs with
up to 13 rows of memory cells (13 refresh address bits). This includes all practical DRAM sizes for
the Intel386 EX microprocessor’s 64 Mbyte address space.
JTAG Test-logic Unit
The JTAG Test-logic Unit provides access to the device pins and to a number of other testable areas
on the device. It is fully compliant with the IEEE 1149.1 standard and thus interfaces with five
dedicated pins: TRST#, TCK, TMS, TDI, and TDO. It contains the Test Access Port (TAP) finite-
state machine, a 4-bit instruction register, a 32-bit identification register, and a single-bit bypass
register. The test-logic unit also contains the necessary logic to generate clock and control signals
for the Boundary Scan chain.
Since the test-logic unit has its own clock and reset signals, it can operate autonomously. While the
rest of the microprocessor is in Reset or Powerdown, the JTAG unit can read or write various
register chains.
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Provides a programmable-interval timer
Provides the bus arbitration logic to gain control of the bus to run refresh cycles
Contains the logic to generate row addresses to refresh DRAM rows individually
Contains the logic to signal the start of a refresh cycle
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