MPC8360VVALFH Freescale Semiconductor, MPC8360VVALFH Datasheet - Page 23

IC MPU PWRQUICC II 740-TBGA

MPC8360VVALFH

Manufacturer Part Number
MPC8360VVALFH
Description
IC MPU PWRQUICC II 740-TBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8360VVALFH

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
667MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
740-TBGA
For Use With
MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Figure 6
6.2.2
Table 21
DDR and DDR2 SDRAM interface.
Freescale Semiconductor
At recommended operating conditions with GV
At recommended operating conditions with GV
MDQS—MDQ/MECC input skew per byte
Notes:
1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 ≤ n ≤ 7)
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
or ECC (MECC[{0...7}] if n = 8).
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
MDQS[n]
MDQ[x]
shows the input timing diagram for the DDR controller.
and
MCK[n]
MCK[n]
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 22
Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
Parameter
Table 20. DDR and DDR2 SDRAM Input AC Timing Specifications Mode
Parameter
provide the output AC timing specifications and measurement conditions for the
8
333 MHz
266 MHz
200 MHz
DD
DD
Figure 6. DDR Input Timing Diagram
of (1.8 or 2.5 V) ± 5%.
of (1.8 V or 2.5 V) ± 5%.
333 MHz
266 MHz
200 MHz
t
t
MCK
Symbol
DISKEW
t
DISKEW
Synchronous Mode
Symbol
t
AOSKEW
t
MCK
1
D0
–1125
–1250
–750
Min
D1
–1.0
–1.1
–1.2
Min
6
t
DISKEW
1125
1250
Max
750
Max
0.2
0.3
0.4
10
DDR and DDR2 SDRAM
Unit
ps
Unit
ns
ns
Notes
Notes
1, 2
2
3
23

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