CS42448-CQZ Cirrus Logic Inc, CS42448-CQZ Datasheet - Page 18

• Manufacturer Part Number: CS42448-CQZ
• Description: IC CODEC 108DB 192KHZ 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42448-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 6 ADC/8 DAC
• Thd Plus Noise: - 98 dB ADC / - 98 dB DAC, - 95 dB ADC / - 95 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1151 - BOARD EVAL FOR CS42448 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1033

18
SWITCHING SPECIFICATIONS - ADC/DAC PORT
Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT C
Figure 4. Serial Audio Interface Slave Mode Timing
Slave Mode
RST pin Low Pulse Width
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Duty Cycle
SCLK High Time
SCLK Low Time
LRCK Rising Edge to SCLK Rising Edge
SCLK Rising Edge to LRCK Falling Edge
SCLK Falling Edge to ADC_SDOUT Output Valid
DAC_SDIN Setup Time Before SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
ADC_SDOUT Hold Time After SCLK Rising Edge
ADC_SDOUT Valid Before SCLK Rising Edge
Master Mode
Output Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SCLK Rising Edge
SCLK Falling Edge to ADC_SDOUT Output Valid
DAC_SDIN Setup Time Before SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
DAC_SDINx
ADC_SDOUTx
LRCK
SCLK
t
dpd
Parameters
t
lcks
t
ds
t
Double-Speed Mode
sckh
t
MSB
MSB
dh
(Note 21)
Quad-Speed Mode
t
sckl
Single-Speed Mode
All Speed Modes
MSB-1
MSB-1
(Note 17)
(Note 18)
(Note 19)
(Note 20)
LOAD
ADC_SDOUT1
DAC_SDIN1
= 15 pF.
Figure 5. TDM Serial Audio Interface Timing
SCLK
LRCK
(input)
(input)
Symbol
t
t
t
t
t
t
t
t
t
t
sckh
t
t
dval
sckl
lcks
dpd
t
t
dh1
dh2
lcks
dpd
t
dh1
F
F
F
F
fss
fsh
ds
dh
ds
s
s
s
s
t
fss
0.512
Min
100
45
50
45
45
16
10
15
45
45
1
4
8
8
5
3
5
5
3
5
-
-
-
-
-
t
MSB
fsh
t
ds
MCLK / 256
t
dh2
64 x Fs
t
Max
sckh
100
200
MSB
50
55
50
55
55
35
55
55
35
5
-
-
-
-
-
-
-
-
-
-
-
-
t
dh1
t
MSB-1
CS42448
dval
t
sckl
DS648F3
MSB-1
Units
MHz
MHz
kHz
kHz
kHz
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
%