CS42448-CQZ Cirrus Logic Inc, CS42448-CQZ Datasheet - Page 27

• Manufacturer Part Number: CS42448-CQZ
• Description: IC CODEC 108DB 192KHZ 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42448-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 6 ADC/8 DAC
• Thd Plus Noise: - 98 dB ADC / - 98 dB DAC, - 95 dB ADC / - 95 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1151 - BOARD EVAL FOR CS42448 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1033

DS648F3
1. VQ = 0 V.
2. Aout bias = VQ.
3. Audible pops.
No Power Transition
1. VQ = 0 V.
2. Aout bias = VQ.
3. Audible pops.
Power-Down Transition
Hardware Mode not supported.
unknown state once all clocks
recommended that the user
control port before applying
setup up the codec via the
Codec will power up in an
and data are valid. It is
1. VQ = VA/2.
2. Aout bias = VQ.
3. DAC outputs muted.
4. No audio signal generated.
MCLK.
No
1. VQ = 0 V.
2. Aout = VQ.
3. No audio signal generated.
4. Control Port Registers reset
to default.
Power-Down (Power Applied)
Analog Output Mute
Figure 12. Audio Output Initialization Flow Chart
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
Access Detected?
Control Port
RST = Low?
Control Port
No Power
Active
No
Registers setup to
ERROR: MCLK/LRCK ratio change
Software Mode
desired settings.
Valid MCLK
Yes
Applied?
Yes
ERROR: Power removed
Yes
No
RST = Low
1. VQ = VA/2.
2. Aout bias = VQ.
3. Audio signal generated per register settings.
No
1. VQ ramp up to VA/2.
2. Aout bias = VQ.
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Sub-Clocks Applied
Normal Operation
Power-Up Ramp
2000 LRCK delay
PDN bit = '1'b?
400 ms delay
MCLK/LRCK
1. VQ = VA/2.
2. Aout bias = VQ + last audio sample.
3. DAC Modulators stop operation.
4. Audible pops.
Ratio?
Valid
Yes
No
ERROR: MCLK removed
Analog Output Freeze
Yes
PopGuard
1. VQ = 0 V.
2. Aout bias = VQ.
3. No audio signal generated.
4. Control Port Registers retain
settings.
PDN bit set
to '1'b
1. VQ ramp down to 0 V.
2. Aout bias = VQ.
®
Power-Down Ramp
Power-Down Mode
250 ms delay
CS42448
27