CS42448-CQZ Cirrus Logic Inc, CS42448-CQZ Datasheet - Page 37

• Manufacturer Part Number: CS42448-CQZ
• Description: IC CODEC 108DB 192KHZ 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42448-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 6 ADC/8 DAC
• Thd Plus Noise: - 98 dB ADC / - 98 dB DAC, - 95 dB ADC / - 95 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1151 - BOARD EVAL FOR CS42448 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1033

DS648F3
4.8
SCL
SDA
Interrupts
The CS42448 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may be configured as an active low or active high CMOS
driver or an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple pe-
ripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See
(Address 19h) (Read Only)” on page
dition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of
level sensitive or edge sensitive modes within the microcontroller, many different configurations are possi-
ble, depending on the needs of the system designer.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10010xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
START
Figure
0
1
CHIP ADDRESS (WRITE)
1
0
25, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
0
2
1
3
0 AD1 AD0 0
4
5
6
7
ACK
8
Figure 25. Control Port Timing, I²C Read
9
INCR
10 11
6
5
MAP BYTE
12 13 14 15
4
51. Each source may be masked off through mask register bits. In ad-
3
2
1
16
0
ACK
STOP
17 18
START
19
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
0
1
0 AD1 AD0 1
25
26 27 28
ACK
7
DATA
0
ACK
DATA +1
7
0
DATA + n
7
0
ACK
CS42448
NO
STOP
“Status
37