CS42528-CQZ Cirrus Logic Inc, CS42528-CQZ Datasheet - Page 61
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CS42528-CQZ
Manufacturer Part Number
CS42528-CQZ
Description
IC CODEC S/PDIF RCVR 64LQFP
Manufacturer
Cirrus Logic Inc
Type
General Purposer
Datasheet
1.CS42528-CQZ.pdf
(91 pages)
Specifications of CS42528-CQZ
Package / Case
64-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
2
Number Of Dac Outputs
8
Conversion Rate
192 KSPS
Interface Type
Serial (SPI)
Resolution
24 bit
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/8 DAC
Thd Plus Noise
- 100 dB ADC / - 100 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1503 - BOARD EVAL FOR CS42528/CS49300
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1038
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Part Number
Manufacturer
Quantity
Price
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Part Number:
CS42528-CQZ
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Cirrus Logic Inc
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DS586F1
6.16
6.16.1 ADC LEFT CHANNEL GAIN (LGAINX)
6.17
6.17.1 ADC RIGHT CHANNEL GAIN (RGAINX)
6.18
6.18.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
SP_SYNC
Reserved
Reserved
7
7
7
ADC Left Channel Gain (address 1Ch)
ADC Right Channel Gain (address 1Dh)
Receiver Mode Control (address 1Eh)
Default = 00h
Function:
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in
The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in
Default = 0
0 - CX & SAI Serial Port timings not in phase
1 - CX & SAI Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the CX & SAI Serial Ports to align and operate in phase. This func-
tion will operate when both ports are running at the same sample rate or when operating at different
sample rates.
Table
Table
Reserved
Reserved
Reserved
6
6
6
17.
17.
Binary Code
001010
000101
000000
110110
110001
001111
111011
DE-EMPH1
RGAIN5
LGAIN5
Table 17. Example ADC Input Gain Settings
5
5
5
DE-EMPH0
RGAIN4
LGAIN4
Decimal Value
4
4
4
+15
+10
-10
-15
+5
-5
0
RGAIN3
LGAIN3
INT1
3
3
3
Volume Setting
RGAIN2
LGAIN2
+15 dB
+10 dB
-10 dB
-15 dB
+5 dB
-5 dB
0 dB
INT0
2
2
2
RGAIN1
LGAIN1
HOLD1
1
1
1
CS42528
RGAIN0
LGAIN0
HOLD0
0
0
0
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