LM4550BVH/NOPB National Semiconductor, LM4550BVH/NOPB Datasheet
LM4550BVH/NOPB
Specifications of LM4550BVH/NOPB
*LM4550BVH/NOPB
LM4550BVH
Available stocks
Related parts for LM4550BVH/NOPB
LM4550BVH/NOPB Summary of contents
Page 1
... Input Frames (Codec to Controller). Multiple codec systems can be built either using the standard AC Link configuration (i.e. of one serial data signal to the Controller per codec) or using a unique National Semiconductor fea- ture for chaining codecs together. This chain feature shares only a single data signal to the controller among multiple codecs. The AC ’ ...
Page 2
www.national.com 2 ...
Page 3
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage ESD Susceptibility (Note 2) pin 3 ESD Susceptibility (Note 3) pin 3 Junction Temperature Electrical Characteristics 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for Vrms unless otherwise specified ...
Page 4
Electrical Characteristics 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for Vrms unless otherwise specified. (Continued) Symbol Parameter Analog to Digital Converters Resolution Dynamic Range (Note 9) Frequency Response Digital to Analog Converters ...
Page 5
Electrical Characteristics 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for Vrms unless otherwise specified. (Continued) Symbol Parameter T Hold Time for codec data input DHOLD T Setup Time for codec SYNC input ...
Page 6
Timing Diagrams Clocks Digital Rise and Fall www.national.com Data Delay, Setup and Hold 20123710 20123712 Power On Reset Cold Reset Warm Reset 6 20123711 Legend 20123730 20123729 20123713 20123714 ...
Page 7
Typical Application FIGURE 1. LM4550B Typical Application Circuit, Single Codec, 1 Vrms inputs APPLICATION HINTS • The LM4550B must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing Diagram • ...
Page 8
www.national.com 8 ...
Page 9
Connection Diagram Pin Descriptions Name Pin Functional Description Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the PC_Beep ...
Page 10
Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. ...
Page 11
Pin Descriptions (Continued) Name Pin Functional Description Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The ...
Page 12
Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal HP_OUT_L 39 O from MIX2 via the Headphone ...
Page 13
Pin Descriptions (Continued) Name Pin Link frame marker and Warm Reset This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In normal operation SYNC kHz positive ...
Page 14
Pin Descriptions (Continued) Name Pin Analog supply DD1 Analog ground SS1 Analog supply 2 DD2 Analog ground 2 SS2 Digital supply DD1 ...
Page 15
Typical Performance Characteristics ADC Frequency Response Line Out Noise Floor (Analog Loopthrough) Headphone Amplifier THD+N vs Frequency (Continued) 20123719 Headphone Amplifier Noise Floor 20123718 20123727 15 DAC Frequency Response 20123720 (Analog Loopthrough) 20123726 Headphone Amplifier THD+N vs Output Power 20123728 ...
Page 16
Volume Output www.national.com Volume Input Sources ADC 16 ...
Page 17
Functional Description GENERAL The LM4550B codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog ...
Page 18
Functional Description REGISTER RESET is performed when any value is written to the RESET register, 00h. It resets all registers to their AC Link Serial Interface Protocol AC LINK OUTPUT FRAME: SDATA_OUT, CONTROLLER OUTPUT TO LM4550B INPUT The AC Link ...
Page 19
AC Link Serial Interface Protocol (Continued) The LM4550B expects to receive data MSB first MSB justified format. SDATA_OUT: Slot 0 – Tag Phase The first bit of Slot 0 is designated the "Valid Frame" bit. If this bit ...
Page 20
AC Link Serial Interface Protocol (Continued) SLOT 2, OUTPUT FRAME Bits Description Control Controller should stuff with 19:4 Register Write zeros if operation is “read” Data 3:0 Reserved Set to "0" SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right ...
Page 21
AC Link Serial Interface Protocol (Continued) from the LM4550B codec. As shown in Figure 3, Input Frames are constructed from thirteen time slots: one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of ...
Page 22
AC Link Serial Interface Protocol (Continued) SLOT 1, INPUT FRAME Bits Description 19 Reserved Stuffed with "0" by LM4550B Status Register Echo of the requested Status 18:12 Index Register address Controller should send Slot 3 Request valid data ...
Page 23
Register Descriptions Default settings are indicated by *. RESET REGISTER (00h) Writing any value to this register causes a Register Reset which changes all registers back to their default values read is performed on this register, the LM4550B ...
Page 24
Register Descriptions SR2:SR0 Source for Right Channel ADC 1 CD input (R) 2 VIDEO input (R) 3 AUX input (R) 4 LINE_IN input (R) 5 Stereo Mix (R) 6 Mono Mix 7 PHONE input Default: 0000h RECORD GAIN REGISTER (1Ch) ...
Page 25
Register Descriptions BIT# BIT Function: Powerdown External Amplifier PowerDown 15 EAPD *0 = Set EAPD Pin to 0 (pin 47) Default:000Fh if ready; otherwise 000Xh EXTENDED AUDIO ID REGISTER (28h) This read-only (X201h) register identifies which AC ’97 Ex- tended ...
Page 26
Register Descriptions dard one SDATA_IN pin per codec. Note, however, that the chained codecs time-share the bandwidth of the SDATA_IN signal under allocation from the controller. The first codec in the chain (nearest the controller) will have access to the ...
Page 27
Improving System Performance The audio codec is capable of dynamic range performance in excess of 90 dB., but the user must pay careful attention to several factors to achieve this. A primary consideration is keeping analog and digital grounds separate, ...
Page 28
Multiple Codecs (Continued) The Codec Identity is determined by the inverting input pins ID1#, ID0# (pins 46 and 45) and can be read as the value of the ID1, ID0 bits (D15, D14) in the Extended Audio ID register, 28h ...
Page 29
... FIGURE 9. Multiple Codecs using Extended AC Link CODEC CHAINING Using National Semiconductor’s unique feature for chaining together codecs, a multiple codec system can be built using fewer interface pins. This Chain feature allows two, three or four codecs to share a single signal input pin at the control- ler ...
Page 30
Multiple Codecs (Continued) Test Modes AC ’97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ATE test mode is activated if SDATA_OUT is ...
Page 31
... BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. ...