LM4550BVH/NOPB National Semiconductor, LM4550BVH/NOPB Datasheet - Page 19

• Manufacturer Part Number: LM4550BVH/NOPB
• Description: IC AC '97 AUDIO CODEC 48-LQFP
• Manufacturer: National Semiconductor
• Type: Audio Codec '97r

Specifications of LM4550BVH/NOPB

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 89
• Voltage - Supply, Analog: 4.2 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 3
• Adc / Dac Resolution: 18bit
• Sampling Rate: 48kSPS
• Interface Type: Serial
• Supply Voltage Range: 3V To 5.5V, 4.2V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM4550BVH; *LM4550BVH/NOPB; LM4550BVH

AC Link Serial Interface Protocol
The LM4550B expects to receive data MSB first, in an MSB
justified format.
SDATA_OUT: Slot 0 – Tag Phase
The first bit of Slot 0 is designated the "Valid Frame" bit. If
this bit is 1, it indicates that the current Output Frame con-
tains at least one slot of valid data and the LM4550B will
check further tag bits for valid data in the expected Data
Slots. With the codec in Primary mode, a controller will
indicate valid data in a slot by setting the associated tag bit
equal to 1. Since it is a two channel codec the LM4550B can
only receive data from four slots in a given frame and so only
checks the valid-data bits for 4 slots. In Primary mode these
tag bits are for: slot 1 (Command Address), slot 2 (Command
Data), slot 3 (PCM data for left DAC) and slot 4 (PCM data
for right DAC).
The last two bits in the Tag contain the Codec ID used to
select the target codec to receive the frame in multiple codec
systems. When the frame is being sent to a codec in one of
the Secondary modes the controller does not use bits 14 and
13 to indicate valid Command Address and Data in slots 1
and 2. Instead, this role is performed by the Codec ID bits –
operation of the Extended AC Link assumes that the control-
ler would not access a secondary codec unless it was pro-
viding valid Command Address and/or Data. When in one of
the secondary modes the LM4550B only checks the tag bits
for the Codec ID and for valid data in the two audio data
slots: slots 3 & 4 for Secondary mode 1, slots 7 & 8 for mode
2 and slots 6 & 9 for mode 3.
When sending an Output Frame to a Secondary mode co-
dec, a controller should set tag bits 14 and 13 to zero.
(Continued)
Bit
15
14
13
FIGURE 5. Start of AC Link Output Frame
Control register
Control register
Description
Valid Frame
address
data
SLOT 0, OUTPUT FRAME
1 = Valid data in at least one
1 = Valid Control Address in
1 = Valid Control Data in Slot
slot.
Slot 1 (Primary codec
only)
2 (Primary codec only)
Comment
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SDATA_OUT: Slot 1 – Read/Write, Control Address
Slot 1 is used by a controller to indicate both the address of
a target register in the LM4550B and whether the access
operation is a register read or register write. The MSB of slot
1 (bit 19) is set to 1 to indicate that the current access
operation is ’read’. Bits 18 through 12 are used to specify the
7-bit register address of the read or write operation. The
least significant twelve bits are reserved and should be
stuffed with zeros by the AC ’97 controller.
SDATA_OUT: Slot 2 – Control Data
Slot 2 is used to transmit 16-bit control data to the LM4550B
when the access operation is ’write’. The least significant
four bits should be stuffed with zeros by the AC ’97 controller.
If the access operation is a register read, the entire slot, bits
19 through 0 should be stuffed with zeros.
18:12
Bits
11:0
Bit
5:2
1,0
12
11
10
19
9
8
7
6
Right DAC data
Right DAC data
Right DAC data
Left DAC data
Left DAC data
Left DAC data
Description
Description
Read/Write
(ID1, ID0)
Not Used
Not Used
Codec ID
Reserved
in Slot 3
in Slot 4
in Slot 6
in Slot 7
in Slot 8
in Slot 9
Register
Address
SLOT 1, OUTPUT FRAME
Controller should stuff this slot
with “0”s
Controller should stuff these
slots with “0”s
The Codec ID (Table 1) selects
the target codec in a
multi-codec system to receive
the control address and data
carried in the Output Frame
1 = Read
0 = Write
Identifies the Status/Command
register for read/write
Controller should set to "0"
1 = Valid PCM Data in Slot 3
1 = Valid PCM Data in Slot 4
1 = Valid PCM Data in Slot 6
1 = Valid PCM Data in Slot 7
1 = Valid PCM Data in Slot 8
1 = Valid PCM Data in Slot 9
(Primary & Secondary 1
modes; Left Channel
audio)
(Primary & Secondary 1
modes; Right Channel
audio)
(Secondary 3 mode;
Center Channel audio)
(Secondary 2 mode; Left
Surround Channel audio)
(Secondary 2 mode;
Right Surround Channel
audio)
(Secondary 3 mode; LFE
Channel audio)
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