LM4550BVH/NOPB National Semiconductor, LM4550BVH/NOPB Datasheet - Page 25

IC AC '97 AUDIO CODEC 48-LQFP

LM4550BVH/NOPB

Manufacturer Part Number
LM4550BVH/NOPB
Description
IC AC '97 AUDIO CODEC 48-LQFP
Manufacturer
National Semiconductor
Type
Audio Codec '97r
Datasheets

Specifications of LM4550BVH/NOPB

Data Interface
Serial
Resolution (bits)
18 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
90 / 89
Voltage - Supply, Analog
4.2 V ~ 5.5 V
Voltage - Supply, Digital
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
8
No. Of Output Channels
3
Adc / Dac Resolution
18bit
Sampling Rate
48kSPS
Interface Type
Serial
Supply Voltage Range
3V To 5.5V, 4.2V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*LM4550BVH
*LM4550BVH/NOPB
LM4550BVH

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Register Descriptions
EXTENDED AUDIO ID REGISTER (28h)
This read-only (X201h) register identifies which AC ’97 Ex-
tended Audio features are supported. The LM4550B features
AMAP (Slot/DAC mappings based on Codec Identity), VRA
(Variable Rate Audio) and ID1, ID0, the Codec Identity bits
used to support multi-codec systems. AMAP is indicated by
a "1" in bit 9, VRA is indicated by a "1" in bit 0. The two
MSBs, ID1 and ID0, show the current Codec Identity as
defined by the Identity pins ID1#, ID0#. Note that the exter-
nal logic connections to ID1#, ID0# (pins 46 and 45) are
inverse in polarity to the value of the Codec Identity (ID1,
ID0) held in bits D15, D14. The AMAP Slot/DAC mappings
are given in Table 1 in the Multiple Codec section. Codec
mode selections are shown in the table below.
Default:000Fh if ready; otherwise 000Xh
BIT#
15
EAPD
BIT
External Amplifier PowerDown
*0 = Set EAPD Pin to 0 (pin 47)
Function: Powerdown
(Continued)
25
EXTENDED AUDIO STATUS/CONTROL REGISTER
(2Ah)
This read/write register provides status and control of the
variable sample rate capabilities in the LM4550B. Setting the
LSB of this register to "1" enables Variable Rate Audio (VRA)
mode and allows DAC and ADC sample rates to be pro-
grammed via registers 2Ch and 32h respectively.
SAMPLE RATE CONTROL REGISTERS (2Ch, 32h)
These read/write registers are used to set the sample rate
for the left and right channels of the DAC (PCM DAC Rate,
2Ch) and the ADC (PCM ADC Rate, 32h). When Variable
Rate Audio is enabled via bit 0 of the Extended Audio
Control/Status register (2Ah), the sample rates can be pro-
grammed, in 1 Hz increments, to be any value from 4 kHz to
48 kHz. The value required is the hexadecimal representa-
tion of the desired sample rate, e.g. 8000
is a list of the most common sample rates and the corre-
sponding register (hex) values.
CHAIN-IN CONTROL REGISTER (74h)
This read/write register is only needed when using the Chain
In feature. This feature goes beyond the AC ’97 specification
and is not required for standard AC Link operation. The two
LSBs of this register default to the Codec Identity (ID1, ID0)
after reset. This default state corresponds to standard AC
Link operation where the output of codec pin 8 (SDATA_IN)
carries the AC Link Input Frames back to the controller from
the codec.
If the two LSBs differ from the Codec Identity (register 28h
describes the Codec Identity), then the signal present at CIN
(pin 48) is switched through to the SDATA_IN (pin 8) output.
In this fashion, Secondary codecs can be chained together
by connecting one codec’s SDATA_IN pin to the next co-
dec’s CIN pin. This has the end result of only requiring a
single SDATA_IN pin at the controller rather than the stan-
NC/DV
NC/DV
Default: 0000h
Pin 46
(ID1#)
GND
GND
VRA
BIT
DD
DD
SR15:SR0
*BB80h
NC/DV
NC/DV
AC44h
1F40h
2B11h
3E80h
5622h
Pin 45
*0 = VRA off (Frame-rate sampling)
(ID0#)
GND
GND
1 = VRA on
Common Sample Rates
DD
DD
D15,28h
(ID1)
0
0
1
1
Function
D14,28h
(ID0)
Sample Rate (Hz)
0
1
0
1
*48000
11025
16000
22050
44100
10
8000
Codec Identity
Primary
Secondary 1
Secondary 2
Secondary 3
= 1F40h. Below
Mode
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