UDA1355H/N2,518 NXP Semiconductors, UDA1355H/N2,518 Datasheet - Page 18

• Manufacturer Part Number: UDA1355H/N2,518
• Description: IC CODEC STER/SUDIO SPDIF 44QFP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1355H/N2,518

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 98
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271552518

NXP Semiconductors
Table 8 Muting to prevent plopping
7.8
The selection of the digital audio input and output formats
and master or slave modes differ for static and
microcontroller mode.
In master mode, when 256f
the digital interface is master, the BCK output clock will be
64f
clock will be 48f
In the static mode the digital audio input formats are:
• I
• LSB-justified; 16 bits
• LSB-justified; 24 bits
• MSB-justified.
The digital audio output formats are:
• I
• MSB-justified.
In the microcontroller mode, the following formats are
independently selectable:
• I
• LSB-justified; 16 bits
2003 Apr 10
Input selection
Select channel 1 source
Select channel 2 source
Select chip mode
PLL is source for the DAC
Crystal is source for the DAC
Select between microcontroller mode and static mode
PLL is source for the DAC
Crystal is source for the DAC
Audio features
Select noise shaper order
Select FSDAC output polarity
Select SPDIF input
Select mixer
Select mixer position
Select crystal clock source
Stereo audio codec with SPDIF interface
2
2
2
s
S-bus
S-bus
S-bus
. In case 384f
Digital audio input and output
OCCASION
s
.
s
output clock is selected, the BCK output
s
output clock is selected and
MT1
−
−
−
−
−
−
−
−
−
−
−
x
MT2
BIT
18
−
−
−
−
−
−
−
−
−
−
−
x
• LSB-justified; 18 bits
• LSB-justified; 20 bits
• LSB-justified; 24 bits
• MSB-justified.
7.9
The UDA1355H has a dedicated reset pin with an internal
pull-down resistor. In this way a Power-on reset circuit can
be made with a capacitor and a resistor at pin RESET. The
external resistor is needed since the pad is 5 V tolerant.
This means that there is a transmission gate in series with
the input and the resistor inside the pad cannot be seen
from the outside world (see Fig.10).
The reset timing is determined by the external pull-down
resistor and the external capacitor which is connected to
pin RESET. At Power-on reset, all the digital sound
processing features and the system controlling features
are set to the default setting of the microcontroller mode.
Since the bit controlling the clock of the synchronous
registers is set to enable, the synchronous registers are
also reset.
MTM
Power-on reset
−
−
x
x
x
x
x
x
x
−
−
x
no mute after selection
no mute after selection
wait until PLL is locked again
no mute after selection
wait until PLL is locked again
no mute after selection
no mute after selection
no mute after selection
PLL is locked again
no mute needed
no mute needed
no mute after selection
DE-MUTE CONDITION
Preliminary specification
UDA1355H