EMC1423-1-AIZL-TR SMSC, EMC1423-1-AIZL-TR Datasheet - Page 21

• Manufacturer Part Number: EMC1423-1-AIZL-TR
• Description: Board Mount Temperature Sensors TRIPLE TEMP SNSR
• Manufacturer: SMSC

Specifications of EMC1423-1-AIZL-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1°C Temperature Sensor with Hardware Thermal Shutdown
Datasheet
SMSC EMC1423/EMC1424
5.3
5.3.1
5.3.2
5.4
The ALERT pin is an open drain output and requires a pull-up resistor to V
operation: interrupt mode and comparator Mode. The mode of the ALERT output is selected via the
ALERT / COMP bit in the Configuration Register (see
ALERT Pin Interrupt Mode
When configured to operate in interrupt mode, the ALERT pin asserts low when an out of limit
measurement (> high limit or < low limit) is detected on any diode or when a diode fault is detected.
The ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit
condition has been removed, the ALERT pin will remain asserted until the appropriate status bits are
cleared.
The ALERT pin can be masked by setting the MASK bit. Once the ALERT pin has been masked, it
will be de-asserted and remain de-asserted until the MASK bit is cleared by the user. Any interrupt
conditions that occur while the ALERT pin is masked will update the Status Register normally.
The ALERT pin is used as an interrupt signal or as an Smbus Alert signal that allows an SMBus slave
to communicate an error condition to the master. One or more ALERT outputs can be hard-wired
together.
ALERT Pin Comparator Mode
When the ALERT pin is configured to operate in comparator mode it will be asserted if any of the
measured temperatures exceeds the respective high limit. The ALERT pin will remain asserted until
all temperatures drop below the corresponding high limit minus the THERM Hysteresis value.
When the ALERT pin is asserted in comparator mode, the corresponding high limit status bits will be
set. Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is
deasserted, the status bits will be automatically cleared.
The MASK bit will not block the ALERT pin in this mode, however the individual channel masks (see
Section
Because of the decode method used to determine the Hardware Thermal Shutdown Limit, it is
important that the pull-up resistance on both the ALERT and SYS_SHDN pins be within the tolerances
shown in
connected to the same 3.3V supply that drives the VDD pin.
For 15ms after power up, the ALERT and SYS_SHDN pins must not be pulled low or the Hardware
Thermal Shutdown Limit will not be decoded properly. If the system requirements do not permit these
conditions, then the ALERT and SYS_SHDN pins must be isolated from their respective busses during
this time.
One method of isolating this pin is shown in
ALERT Output
ALERT and SYS_SHDN Pin Considerations
6.12) will prevent the respective channel from asserting the ALERT pin.
Table
5.3. Additionally, the pull-up resistor on the ALERT and SYS_SHDN pins must be
DATASHEET
21
Figure
5.4.
Section
6.4).
DD
and has two modes of
Revision 1.36 (07-02-09)