EMC1073-A-AIZL-TR SMSC, EMC1073-A-AIZL-TR Datasheet - Page 29

• Manufacturer Part Number: EMC1073-A-AIZL-TR
• Description: Board Mount Temperature Sensors SMBus Temp Sensor Selectable Address
• Manufacturer: SMSC

Specifications of EMC1073-A-AIZL-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADDR
03h
09h
ADDR
02h
Multiple Channel 1°C Temperature Sensors with Selectable Address
Datasheet
SMSC EMC1073 / EMC1074
6.3
6.4
R/W
R/W
R/W
R
Configuration
REGISTER
The Status Register reports general error conditions. To identify specific channels, refer to
Section
cleared when the appropriate High Limit, Low Limit, or THERM Limit register has been read or cleared.
Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either
the ALERT or THERM pins to be asserted.
Bit 4 - HIGH - This bit is set when any of the temperature channels exceeds its programmed high limit.
See the High Limit Status Register for specific channel information
will assert the ALERT pin.
Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low
limit. See the Low Limit Status Register for specific channel information
bit will assert the ALERT pin.
Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode
channels. See the External Diode Fault Register for specific channel information
set, this bit will assert the ALERT pin.
Bit 1 - THERM - This bit is set when the any of the temperature channels exceeds its programmed
THERM limit. See the THERM Limit Status Register for specific channel information
When set, this bit will assert the THERM pin.
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.
Bit 6 - RUN / STOP - Controls Active/Standby modes.
Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.
Status Register
Configuration Register
REGISTER
‘0’ (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the ALERT
pin will be asserted.
‘1’ - The ALERT pin is masked. It will not be asserted for any interrupt condition unless it is
configured as a secondary THERM pin. The Status Registers will be updated normally.
‘0’ (default) - The device is in Active mode and converting on all channels.
‘1’ -The device is in Standby mode and not converting.
‘0’ (default) - The ALERT pin acts in interrupt mode as described in
Interrupt
Status
6.10,
Mode".
Section
MASK_
ALL
BUSY
B7
B7
6.14,
RUN /
STOP
Table 6.4 Configuration Register
B6
B6
-
Section
Table 6.3 Status Register
DATASHEET
ALERT/
COMP
6.15, and
B5
B5
-
29
HIGH
B4
Section
B4
1
LOW
B3
6.16. The individual Status Register bits are
B3
1
FAULT
B2
RANGE
B2
(Section
(Section
Section 5.3.1, "ALERT Pin
THERM
B1
DAVG_
6.14). When set, this bit
DIS
B1
Revision 1.39 (10-11-10)
(Section
6.15). When set, this
B0
-
(Section
APDD
B0
6.10). When
DEFAULT
6.16).
DEFAULT
00h
18h