EMC2305-1-AP-TR SMSC, EMC2305-1-AP-TR Datasheet - Page 41

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EMC2305-1-AP-TR

Manufacturer Part Number
EMC2305-1-AP-TR
Description
Industrial Temperature Sensors Penta RPM-Based PWN Fan Speed Controller
Manufacturer
SMSC
Datasheet

Specifications of EMC2305-1-AP-TR

Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EMC2305-1-AP-TR
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
EMC2305-1-AP-TR
0
ADDR
36h
46h
56h
66h
76h
Multiple RPM-Based PWM Fan Controller for Five Fans
Datasheet
SMSC EMC2305
5.12
R/W
R/W
R/W
R/W
R/W
R/W
GAIND OR GAINP OR GAINI [1:0]
1
0
0
1
1
DRIVE_FAIL_CNTX[1:0]
1
1
1
The Fan Spin Up Configuration registers control the settings of Spin Up Routine. The Fan Spin Up
Configuration registers are software locked.
Bit 7 - 6 - DRIVE_FAIL_CNTx[1:0] - Determines how many update cycles are used for the Drive Fail
detection function as shown in
the desired tach target.
Bit 5 - NOKICKx - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of
the programmed spin up time before driving it at the programmed level.
Fan Spin Up Configuration Registers
Fan 1 Spin Up
Fan 2 Spin up
Fan 3 Spin up
Fan 4 Spin up
Fan 5 Spin up
Configuration
Configuration
Configuration
Configuration
Configuration
‘0’ (default) - The Spin Up Routine will drive the fan driver to 100% for 1/4 of the programmed spin
up time before reverting to the programmed spin level.
REGISTER
Table 5.19 Fan Spin Up Configuration Registers
Table 5.20 DRIVE_FAIL_CNT[1:0] Bit Decode
DRIVE_FAIL_
DRIVE_FAIL_
DRIVE_FAIL_
DRIVE_FAIL_
DRIVE_FAIL_
B7
CNT1 [1:0]
CNT2 [1:0]
CNT3 [1:0]
CNT4 [1:0]
CNT5 [1:0]
0
0
1
0
1
Table 5.18 Gain Decode (continued)
0
0
1
B6
Table
DATASHEET
5.20. This circuitry determines whether the fan can be driven to
Disabled - the Drive Fail detection circuitry is disabled (default)
16 - the Drive Fail detection circuitry will count for 16 update
periods
32 - the Drive Fail detection circuitry will count for 32 update
periods
64 - the Drive Fail detection circuitry will count for 64 update
periods
NOKICK1
NOKICK2
NOKICK3
NOKICK4
NOKICK5
B5
41
NUMBER OF UPDATE PERIODS
B4
SPIN_LVL1[2:0]
SPIN_LVL2[2:0]
SPIN_LVL3[2:0]
SPIN_LVL4[2:0]
SPIN_LVL5[2:0]
RESPECTIVE GAIN FACTOR
B3
4x (default)
B2
8x
SPINUP_TIME
SPINUP_TIME
SPINUP_TIME
SPINUP_TIME
SPINUP_TIME
B1
Revision 1.2 (03-22-10)
1 [1:0]
2 [1:0]
4 [1:0]
5 [1:0]
3[1:0]
B0
DEFAULT
19h
19h
19h
19h
19h

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