AD1981BJST-REEL Analog Devices Inc, AD1981BJST-REEL Datasheet - Page 14

• Manufacturer Part Number: AD1981BJST-REEL
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981BJST-REEL

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.5V
• Single Supply Voltage (max): 3.47/5.5V
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant
• Other names: AD1981BJST-REEL; AD1981BJST-REELTR

AD1981B
HEADPHONE VOLUME REGISTER
Index 0x04
This register controls the headphone volume controls for both stereo channels and the mute bit. Each volume subregister contains five
bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility,
whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback,
all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples.
Reg
No.
0x04
1
Table 11.
Bit
RHV [4:0]
RM
LHV [4:0]
HPM
Table 12. Volume Settings for Master and Headphone
Reg. 0x76
MSPLT
0
0
0
0
0
1
1
1
1
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved.
X is a wild card and has no effect on the value.
1
Name
Headphone
Volume
D15
0
0
0
0
1
0
1
1
Mnemonic
Right Headphone
Volume Control
Right-Channel Mute
Left Headphone
Volume Control
Headphone Volume
Mute
D15
HPM
Write
00 0000
00 1111
01 1111
1X XXXX
XX XXXX
1X XXXX
XX XXXX
XX XXXX
D14
X
Left-Channel Volume D [13:8]
Readback
00 0000
00 1111
01 1111
01 1111
XX XXXX
01 1111
XX XXXX
XX XXXX
D13
X
Function
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
HPM bit. Otherwise, this bit always reads 0 and has no effect when set to 1.
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
D12
LHV4
Control Bits Master Volume (0x02) and Headphone Volume (0x04)
Function
0 dB Gain
−22.5 dB Gain
−46.5 dB Gain
−46.5 dB Gain
−∞ dB Gain, Muted
−46.5 dB Gain
−∞ dB Gain, Left Only Muted
−∞ dB Gain, Left Muted
D11
LHV3
D10
LHV2
Rev. C | Page 14 of 32
D9
LHV1
D8
LHV0
D7
RM
D7
X
X
X
X
X
1
0
1
1
1
D6
X
Write
00 0000
00 1111
01 1111
1X XXXX
XX XXXX
XX XXXX
XX XXXX
XX XXXX
D5
X
Right-Channel Volume D [5:0]
D4
RHV4
00 0000
00 1111
01 1111
01 1111
XX XXXX
XX XXXX
XX XXXX
Readback
XX XXXX
D3
RHV3
D2
RHV2
Function
0 dB Gain
−22.5 dB Gain
−46.5 dB Gain
−46.5 dB Gain
−∞ dB Gain, Muted
−∞ dB Gain, Right Only Muted
−46.5 dB Gain
−∞ dB Gain, Right Muted
D1
RHV1
D0
RHV0
Default
0x8000