AD1981BJST-REEL Analog Devices Inc, AD1981BJST-REEL Datasheet - Page 26

• Manufacturer Part Number: AD1981BJST-REEL
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981BJST-REEL

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.5V
• Single Supply Voltage (max): 3.47/5.5V
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant
• Other names: AD1981BJST-REEL; AD1981BJST-REELTR

AD1981B
EQ DATA REGISTER
Index 0x62
Reg
No.
0x62
Table 37.
Bit
CFD [15:0]
MIXER ADC, INPUT GAIN REGISTER
Index 0x64
Reg
No.
0x64
1
Table 38.
Bit
RMG [3:0]
RM
LMG [3:0]
MXM
Table 39. Settings for Mixer ADC, Input Gain
Reg. 0x76
MSPLT
0
0
0
1
1
1
1
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
bits in the EQ Cntrl Register (0x60). Data is written to memory only if the EQM bit (Register 0x60, Bit 15) is asserted.
If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 39 for examples.
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
X is a wild card and has no effect on the value.
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA
Name
EQ
Data
1
Name
Mixer ADC,
Volume
D15
0
0
1
0
1
1
D15
CFD15
Mnemonic
Right Mixer Gain
Control
Right-Channel Mute
Left Mixer Gain Control
Mixer Gain Register
Mute
Mnemonic
Coefficient Data
Write
1111
0000
XXXX
1111
XXXX
XXXX
D15
MXM
D14
CFD14
Left-Channel Mixer Gain D [11:8]
D14
X
Readback
1111
0000
XXXX
1111
XXXX
XXXX
D13
CFD13
D13
X
D12
CFD12
D12
X
Function
This register controls the gain into the mixer ADC from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from
the MXM bit. Otherwise, this bit always reads 0 and has no affect when set to 1.
This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
0 = Unmuted.
1 = Muted (reset default).
Function
The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
Function
22.5 dB Gain
0 dB Gain
−∞ dB Gain, Muted
22.5 dB Gain
−∞ dB Gain, Left Only Muted
−∞ dB Gain, Left Muted
D11
CFD11
D11
LMG3
Control Bits Mixer ADC, Input Gain (0x64)
D10
CFD10
D10
LMG2
Rev. C | Page 26 of 32
D9
CFD9
D9
LMG1
D8
CFD8
D8
LMG0
D7
CFD7
D7
X
X
X
1
0
1
D7
RM
1
1
D6
CFD6
Write
1111
0000
XXXX
XXXX
1111
XXXX
D6
X
D5
X
Right-Channel Mixer Gain D [3:0]
D5
CFD5
Readback
1111
0000
XXXX
XXXX
1111
XXXX
D4
X
D4
CFD4
D3
RMG3
D3
CFD3
Function
22.5 dB Gain
0 dB Gain
−∞ dB Gain, Muted
−∞ dB Gain, Right Only Muted
22.5 dB Gain
−∞ dB Gain, Right Muted
D2
RMG2
D2
CFD2
D1
RMG1
D1
CFD1
D0
RMG0
D0
CFD0
Default
0x8000
Default
0x0000